coreboot-gerrit March 2021

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Change in coreboot[master]: tests: Add lib/compute_ip_checksum-test test case
by Paul Fagerburg (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Martin Roth, jacz(a)semihalf.com, Jan Dabros. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51089 ) Change subject: tests: Add lib/compute_ip_checksum-test test case ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61c578ec93837cb2581a1ab9e2f3db2a0dd69f3d Gerrit-Change-Number: 51089 Gerrit-PatchSet: 2 Gerrit-Owner: jacz(a)semihalf.com Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: jacz(a)semihalf.com Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Tue, 02 Mar 2021 00:04:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add new IRQ module
by build bot (Jenkins) (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Nico Huber. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49408 ) Change subject: soc/intel/common: Add new IRQ module ...................................................................... Patch Set 16: (2 comments) File src/soc/intel/common/block/irq/irq.c: https://review.coreboot.org/c/coreboot/+/49408/comment/fa00056d_391b7ff9 PS16, Line 106: static enum pci_pin find_shareable_pin(enum pci_pin fn_pin_map[MAX_FNS], please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49408/comment/09805d34_6d422046 PS16, Line 224: printk(BIOS_ERR, "ERROR: %s: No free pins left for UNIQUE IRQ\n", __func__); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/49408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c Gerrit-Change-Number: 49408 Gerrit-PatchSet: 16 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 02 Mar 2021 00:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
by Tim Wawrzynczak (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51159 ) Change subject: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT ...................................................................... soc/intel/common/block/irq: Add support for intel_write_pci0_PRT Add a new function to fill out the data structures necessary to generate a _PRT table. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62 --- M src/soc/intel/common/block/include/intelblocks/irq.h M src/soc/intel/common/block/irq/irq.c 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/51159/1 diff --git a/src/soc/intel/common/block/include/intelblocks/irq.h b/src/soc/intel/common/block/include/intelblocks/irq.h index 8548f1e..d41fcf4 100644 --- a/src/soc/intel/common/block/include/intelblocks/irq.h +++ b/src/soc/intel/common/block/include/intelblocks/irq.h @@ -37,5 +37,7 @@ const struct pci_irq_entry *assign_pci_irqs(size_t *num); const struct soc_irq_constraints *soc_irq_constraints(void); +size_t generate_pin_irq_map(struct slot_pin_irq_map pin_irq_map[32][4], + struct pirq_map *pirq_map); #endif /* SOC_INTEL_COMMON_IRQ_H */ diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c index cb004aa..62fbb12 100644 --- a/src/soc/intel/common/block/irq/irq.c +++ b/src/soc/intel/common/block/irq/irq.c @@ -5,6 +5,7 @@ #include <device/pci.h> #include <intelblocks/gpio.h> #include <intelblocks/irq.h> +#include <intelblocks/lpc_lib.h> #include <soc/irq.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <string.h> @@ -366,3 +367,34 @@ return count; } + +size_t generate_pin_irq_map(struct slot_pin_irq_map pin_irq_map[32][4], + struct pirq_map *pirq_map) +{ + const uint8_t *legacy_pirq_routing; + size_t num_devs = 0; + size_t pirq_routes; + size_t i; + + memset(pin_irq_map, 0, sizeof(struct slot_pin_irq_map[32][4])); + memset(pirq_map, 0, sizeof(*pirq_map)); + + pirq_map->type = PIRQ_GSI; + legacy_pirq_routing = lpc_get_pch_pirq_routing(&pirq_routes); + for (i = 0; i < MAX_PIRQS && i < pirq_routes; i++) + pirq_map->gsi[i] = legacy_pirq_routing[i]; + + for (i = 0; i < entry_count; i++) { + unsigned int slot = PCI_SLOT(entries[i].devfn); + unsigned int pin_idx = entries[i].pin - PCI_INT_A; + if (!pin_irq_map[slot][pin_idx].gsi && !pin_irq_map[slot][pin_idx].pirq) { + pin_irq_map[slot][pin_idx].gsi = entries[i].irq; + + /* Map INTA->PIRQ_A, INTB->PIRQ_B, INTC->PIRQ_C, INTD->PIRQ_D */ + pin_irq_map[slot][pin_idx].pirq = (enum pirq)entries[i].pin; + ++num_devs; + } + } + + return num_devs; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/51159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62 Gerrit-Change-Number: 51159 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Use new acpigen_write_PRT_*_entry functions
by Tim Wawrzynczak (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51158 ) Change subject: sb/intel/common: Use new acpigen_write_PRT_*_entry functions ...................................................................... sb/intel/common: Use new acpigen_write_PRT_*_entry functions Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I9f573b9bd40260ab963c5a4a965a6ac483af91ec --- M src/southbridge/intel/common/acpi_pirq_gen.c 1 file changed, 7 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/51158/1 diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 6100be8..04edcf6 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -52,20 +53,16 @@ pirq = pci_int_mapping[pci_dev][int_pin]; if (pirq == PIRQ_NONE) continue; - acpigen_write_package(4); - acpigen_write_dword((pci_dev << 16) | 0xffff); - acpigen_write_byte(int_pin); + if (emit == EMIT_APIC) { - acpigen_write_zero(); - acpigen_write_dword(16 + pirq - PIRQ_A); + const unsigned int gsi = 16 + pirq - PIRQ_A; + acpigen_write_PRT_GSI_entry(pci_dev, int_pin, gsi); } else { snprintf(buffer, sizeof(buffer), - "%s.LNK%c", - lpcb_path, 'A' + pirq - PIRQ_A); - acpigen_emit_namestring(buffer); - acpigen_write_dword(0); + "%s.LNK%c", + lpcb_path, 'A' + pirq - PIRQ_A); + acpigen_write_PRT_source_entry(pci_dev, int_pin, buffer, 0); } - acpigen_pop_len(); } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/51158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f573b9bd40260ab963c5a4a965a6ac483af91ec Gerrit-Change-Number: 51158 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Enable support for common IRQ block
by Tim Wawrzynczak (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Nick Vaccaro. Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Nick Vaccaro, Aamir Bohra, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49409 to look at the new patch set (#12). Change subject: soc/intel/tigerlake: Enable support for common IRQ block ...................................................................... soc/intel/tigerlake: Enable support for common IRQ block Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows tigerlake boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ieb241f2b91af52a7e2d0efe997d35732882ac463 --- M src/soc/intel/tigerlake/Kconfig D src/soc/intel/tigerlake/acpi/pci_irqs.asl M src/soc/intel/tigerlake/acpi/southbridge.asl M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 151 insertions(+), 165 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/49409/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/49409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb241f2b91af52a7e2d0efe997d35732882ac463 Gerrit-Change-Number: 49409 Gerrit-PatchSet: 12 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add new IRQ module
by Tim Wawrzynczak (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Nico Huber. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Duncan Laurie, Arthur Heymans, Aamir Bohra, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49408 to look at the new patch set (#16). Change subject: soc/intel/common: Add new IRQ module ...................................................................... soc/intel/common: Add new IRQ module The Intel FSP provides a default set of IO-APIC IRQs for PCI devices, if the DevIntConfigPtr UPD is not filled in. However, the FSP has a list of rules that the input IRQ table must conform to: 1) One entry per slot/function 2) Functions using PIRQs must use IOxAPIC IRQs 16-23 3) Single-function devices must use INTA 4) Each slot must have consistent INTx<->PIRQy mappings 5) Some functions have special interrupt pin requirements 6) PCI Express RPs must be assigned in a special way (FIXED_INT_PIN) 7) Some functions require a unique IRQ number 8) PCI functions must avoid sharing an IRQ with a GPIO pad which routes its IRQ through IO-APIC. Since the FSP has no visibility into the actual GPIOs used on the board when GpioOverride is selected, IRQ conflicts can occur between PCI devices and GPIOs. This patch gives SoC code the ability to generate a table of PCI IRQs that will meet the FSPs rules and also not conflict with GPIO IRQs. BUG=b:171580862 TEST=Boot with patch series on volteer, verify IO-APIC IRQs in `/proc/interrupts` match what is expected. No `GSI INT` or `could not derive routing` messages seen in `dmesg` output. Verified TPM, touchpad, touchscreen IRQs all function as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c --- A src/soc/intel/common/block/include/intelblocks/irq.h A src/soc/intel/common/block/irq/Kconfig A src/soc/intel/common/block/irq/Makefile.inc A src/soc/intel/common/block/irq/irq.c 4 files changed, 418 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/49408/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/49408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c Gerrit-Change-Number: 49408 Gerrit-PatchSet: 16 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Tim Wawrzynczak (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Angel Pons, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50857 to look at the new patch set (#7). Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... sb/intel/common: Refactor _PRT generation to support GSI-based tables Newer Intel SoCs also support _PRT tables, but they route PCI devices to more than just PIRQs, and statically specify IRQs insteade of using link devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this additional use case. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 --- M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/acpi_pirq_gen.h M src/southbridge/intel/common/rcba_pirq.c 3 files changed, 134 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/50857/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: acpi: Add acpigen_write_{a}pic_* helpers for generating _PRT entries
by Tim Wawrzynczak (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Arthur Heymans. Hello Lance Zhao, build bot (Jenkins), Furquan Shaikh, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51107 to look at the new patch set (#3). Change subject: acpi: Add acpigen_write_{a}pic_* helpers for generating _PRT entries ...................................................................... acpi: Add acpigen_write_{a}pic_* helpers for generating _PRT entries Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ia666bd0e5db40d7873532dc22bc89be9854b903a --- M src/acpi/acpigen_pci.c M src/include/acpi/acpigen_pci.h 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/51107/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/51107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia666bd0e5db40d7873532dc22bc89be9854b903a Gerrit-Change-Number: 51107 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add function to lpc_lib to return PIRQ routing
by Tim Wawrzynczak (Code Review) 02 Mar '21

02 Mar '21

Tim Wawrzynczak has restored this change. ( https://review.coreboot.org/c/coreboot/+/50858 ) Change subject: soc/intel/common: Add function to lpc_lib to return PIRQ routing ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/50858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib215fba54573c50a88aa4584442bd8d27ae017be Gerrit-Change-Number: 50858 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: restore

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Change in coreboot[master]: tests: Add lib/crc_byte-test test case
by Paul Fagerburg (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Martin Roth, jacz(a)semihalf.com, Jan Dabros. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51088 ) Change subject: tests: Add lib/crc_byte-test test case ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9016cd7825cb681fd200b23dd362ca24acf69192 Gerrit-Change-Number: 51088 Gerrit-PatchSet: 2 Gerrit-Owner: jacz(a)semihalf.com Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: jacz(a)semihalf.com Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Mon, 01 Mar 2021 23:49:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2021