coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/intel/shadowmountain: Add the ASL code
by V Sowmya (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: V Sowmya, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra. Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49733 to look at the new patch set (#3). Change subject: mb/intel/shadowmountain: Add the ASL code ...................................................................... mb/intel/shadowmountain: Add the ASL code This patch includes the DSDT ASL code for shadowmountain board. BUG=b:175808146 TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e --- M src/mainboard/intel/shadowmountain/dsdt.asl 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/49733/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e Gerrit-Change-Number: 49733 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/shadowmountain: Add the romstage code
by V Sowmya (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Balaji Manigandan, Aamir Bohra. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49731 ) Change subject: mb/intel/shadowmountain: Add the romstage code ...................................................................... Patch Set 2: (3 comments) File src/mainboard/intel/shadowmountain/spd/Makefile.inc: https://review.coreboot.org/c/coreboot/+/49731/comment/5a4e95b2_d9b22d4f PS1, Line 4: SPD_SOURCES += empty # 0b001 > u don't need empty SPD, please remove Done File src/mainboard/intel/shadowmountain/spd/empty.spd.hex: PS1: > There should be an empty SPD somewhere else. Removed it. File src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/49731/comment/d495b82c_bf103c26 PS1, Line 22: # Enable PCH PCIE RP 5 using CLK 1 : register "PchPcieRpEnable[4]" = "1" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcUsage[1]" = "0x4" : register "PcieRpClkReqDetect[4]" = "1" : : # Enable NVMe PCIE 9 using clk 0 : register "PchPcieRpEnable[8]" = "1" : register "PcieRpLtrEnable[8]" = "1" : register "PcieClkSrcUsage[0]" = "8" : register "PcieClkSrcClkReq[0]" = "0" : : # Enable SD Card PCIE 8 using clk 3 : register "PchPcieRpEnable[7]" = "1" : register "PcieRpLtrEnable[7]" = "1" : register "PcieRpHotPlug[7]" = "1" : register "PcieClkSrcUsage[3]" = "7" : register "PcieClkSrcClkReq[3]" = "3" > Note: This will need to be adapted once CB:48340 lands Yes, i will push a separate CL for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/49731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a Gerrit-Change-Number: 49731 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 22:34:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Add bootblock and verstage code
by V Sowmya (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Martin Roth, Tim Wawrzynczak, Sugnan Prabhu S, Angel Pons, Balaji Manigandan, Aamir Bohra. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49479 ) Change subject: mb/intel/shadowmountain: Add bootblock and verstage code ...................................................................... Patch Set 6: (1 comment) File src/mainboard/intel/shadowmountain/Kconfig: https://review.coreboot.org/c/coreboot/+/49479/comment/4bbeec44_9fa1a32d PS5, Line 24: default y > abuild has an option to enable building for CHROMEOS, and Jenkins tests boards with and without this […] @Angel, I tried building for !chromeos also (https://review.coreboot.org/c/coreboot/+/49056) and i didn't see any failures but to align with this last review comment (https://review.coreboot.org/c/coreboot/+/49056/4//COMMIT_MSG#7) i removed the default and selected it under board config. -- To view, visit https://review.coreboot.org/c/coreboot/+/49479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Gerrit-Change-Number: 49479 Gerrit-PatchSet: 6 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 22:34:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: V Sowmya <v.sowmya(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Add the ASL code
by V Sowmya (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: V Sowmya, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra. Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49733 to look at the new patch set (#2). Change subject: mb/intel/shadowmountain: Add the ASL code ...................................................................... mb/intel/shadowmountain: Add the ASL code This patch includes the ASL code for shadowmountain board. BUG=b:175808146 TEST= Boot shadowmountain board, dump and verify the ASL entries. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e --- M src/mainboard/intel/shadowmountain/dsdt.asl 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/49733/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e Gerrit-Change-Number: 49733 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/shadowmountain: Add the ramstage code
by V Sowmya (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Martin Roth, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49732 to look at the new patch set (#2). Change subject: mb/intel/shadowmountain: Add the ramstage code ...................................................................... mb/intel/shadowmountain: Add the ramstage code This patch includes the ramstage changes for the shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7 --- M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/intel/shadowmountain/Makefile.inc A src/mainboard/intel/shadowmountain/ec.c A src/mainboard/intel/shadowmountain/mainboard.c A src/mainboard/intel/shadowmountain/smihandler.c M src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c A src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c A src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h 11 files changed, 761 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/49732/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7 Gerrit-Change-Number: 49732 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/shadowmountain: Add the romstage code
by V Sowmya (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Martin Roth, Tim Wawrzynczak, Balaji Manigandan, Aamir Bohra. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Balaji Manigandan, Aamir Bohra, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49731 to look at the new patch set (#2). Change subject: mb/intel/shadowmountain: Add the romstage code ...................................................................... mb/intel/shadowmountain: Add the romstage code This patch includes the romstage changes for the shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early ramstage. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a --- M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/intel/shadowmountain/Makefile.inc A src/mainboard/intel/shadowmountain/romstage.c A src/mainboard/intel/shadowmountain/spd/Makefile.inc A src/mainboard/intel/shadowmountain/spd/shadowmountain_lp5.spd.hex M src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/shadowmountain/variants/baseboard/memory.c 9 files changed, 169 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/49731/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a Gerrit-Change-Number: 49731 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/shadowmountain: Add bootblock and verstage code
by V Sowmya (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: V Sowmya, Martin Roth, Tim Wawrzynczak, Sugnan Prabhu S, Balaji Manigandan, Aamir Bohra. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Sugnan Prabhu S, Tim Wawrzynczak, Angel Pons, Subrata Banik, Balaji Manigandan, Aamir Bohra, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49479 to look at the new patch set (#6). Change subject: mb/intel/shadowmountain: Add bootblock and verstage code ...................................................................... mb/intel/shadowmountain: Add bootblock and verstage code This patch includes the bootblock and verstage changes for shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early romstage. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a --- M src/mainboard/intel/shadowmountain/Kconfig A src/mainboard/intel/shadowmountain/Makefile.inc A src/mainboard/intel/shadowmountain/bootblock.c A src/mainboard/intel/shadowmountain/chromeos.c A src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb A src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c A src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h 9 files changed, 283 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/49479/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/49479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Gerrit-Change-Number: 49479 Gerrit-PatchSet: 6 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines
by Felix Held (Code Review) 01 Feb '21

01 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50205 ) Change subject: soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines ...................................................................... soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines This define was copied over from Stoneyridge, but isn't present on Picasso and newer. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba --- M src/soc/amd/picasso/include/soc/southbridge.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/50205/1 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index f7edaad..d45c3b0 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -74,8 +74,6 @@ #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) -#define PM_USB_ENABLE 0xef -#define PM_USB_ALL_CONTROLLERS 0x7f /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/50205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba Gerrit-Change-Number: 50205 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: First pass GPIO configuriation for Guybrush
by Mathew King (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Furquan Shaikh, Angel Pons. Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50091 ) Change subject: mb/google/guybrush: First pass GPIO configuriation for Guybrush ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/50091/comment/982c3323_dcffe04e PS5, Line 10: /* PWR_BTN_L */ > Save for AGPIO/EGPIO, the comments match the macros. Yes they will be updated when I do my next GPIO pass and will match the net names when enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/50091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8211dbc3de09a61f264a0e5d44d1eac703b83c9 Gerrit-Change-Number: 50091 Gerrit-PatchSet: 5 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 22:04:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mathew King <mathewk(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: First pass GPIO configuriation for Guybrush
by Angel Pons (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Furquan Shaikh, Mathew King. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50091 ) Change subject: mb/google/guybrush: First pass GPIO configuriation for Guybrush ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/50091/comment/31adf6c8_cf39d89c PS5, Line 10: /* PWR_BTN_L */ > These correspond to net names on the schematic and are helpful on other boards. Save for AGPIO/EGPIO, the comments match the macros. -- To view, visit https://review.coreboot.org/c/coreboot/+/50091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8211dbc3de09a61f264a0e5d44d1eac703b83c9 Gerrit-Change-Number: 50091 Gerrit-PatchSet: 5 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Feb 2021 21:51:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mathew King <mathewk(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2021