Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31250 )
Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Furquan, do you remember what pads exactly were overwritten? I'm surprised there was no problem in skl/kbl, because FSP-S configures some pads, too, there, based on a few UPDs (S0ix, HDA/Azalia, Clkreq, ...). That's what is happening on CNL, too. See CB:45211
I doubt that we will get any "fix" for this in FSP because it seems to be absolutely intended. - I'm not saying I like what FSP does, though. ;)
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50048 )
Change subject: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration
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Patch Set 4:
(2 comments)
File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/50048/comment/abe7cf4f_9e0a5623
PS4, Line 158: params->PchLockDownRtcMemoryLock = 0;
OK: Unconditionally set later in this function.
File src/soc/intel/skylake/finalize.c:
https://review.coreboot.org/c/coreboot/+/50048/comment/ba66154d_8d034544
PS4, Line 79: config
No longer used.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50045 )
Change subject: soc/intel/skylake: Set "PEG?Enable" UPD directly
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Patch Set 4:
(2 comments)
Patchset:
PS4:
I'm still not convinced this patch can really improve much. What's the reason for this change?
File src/soc/intel/skylake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/50045/comment/d579fdb0_deed1fbb
PS4, Line 174: if (dev && dev->enabled) {
Now this will leave FSP UPDs unprogrammed for disabled PEG RPs. If you want to avoid rewriting the UPD, you have to write the desired values in one statement, and actually remove the write in the if-block:
m_cfg->Peg0Enable = dev && dev->enabled ? 2 : 0;
if (m_cfg->Peg0Enable) { ...
How many nanoseconds does this shave off the boot time, though?
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50101 )
Change subject: hatch: Modify genesis PcieClkSrc settings
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Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50101/comment/2e388535_c775d679
PS2, Line 9: to work around issue with Longsys SSD
I think it would be good to provide some context as to why the change is being made. I understand that you are submitting this change on behalf of Quanta, but a quick explanation as to why this change is required would be very helpful.
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Change subject: hatch: Update fan and thermal settings for ambassador
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Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50100/comment/5c938d91_432be4a8
PS2, Line 7: hatch: Update fan and thermal settings for ambassador, per recommendations from Quanta.
> Updated word wrapping; please let me know if I need to remove the CrOS-specific metadata as well
Cros-specific metadata is fine.
Patchset:
PS3:
Change looks okay to me. It would be good if someone more familiar with the project can ensure that the settings make sense.
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Benjamin Doron has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50046 )
Change subject: soc/intel/skylake: Remove unnecessary DdrFreqLimit override
......................................................................
Abandoned
Not depending on FSP default
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Change subject: soc/intel/skylake: Remove X2ApicOptOut UPD override
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Abandoned
Not depending on FSP default
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Change subject: soc/intel/skylake: Set "PEG?Enable" UPD directly
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50045/comment/de0a6958_e9622772
PS3, Line 9: This configuration duplicates FSP defaults.
> I agree, we should not rely on someone else defaults.
Ack
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