Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31250 )
Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> I had used this diff:
>
> diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
> index 294218c42f..34d46bfe4d 100644
> --- a/src/soc/intel/common/block/gpio/gpio.c
> +++ b/src/soc/intel/common/block/gpio/gpio.c
> @@ -265,10 +265,10 @@ static void gpio_configure_pad(const struct pad_config *cfg)
> soc_pad_conf &= mask[i];
> soc_pad_conf |= pad_conf & ~mask[i];
>
> - if (IS_ENABLED(CONFIG_DEBUG_GPIO))
> + if (soc_pad_conf != pad_conf)
> printk(BIOS_DEBUG,
> - "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
> - " : 0x%08x]\n",
> + "%d: gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
> + " : 0x%08x]\n", cfg->pad,
> comm->port, relative_pad_in_comm(comm, cfg->pad), i,
> pad_conf,/* old value */
> cfg->pad_config[i],/* value passed from gpio table */
>
> And this was the output I got for hatch:
>
> 17: gpio_padcfg [0x6e, 17] DW0 [0x40000600 : 0x40000400 : 0x40000400]
> 51: gpio_padcfg [0x6e, 51] DW1 [0x00003c6c : 0x00000000 : 0x0000006c]
> 52: gpio_padcfg [0x6e, 52] DW1 [0x00003c6d : 0x00000000 : 0x0000006d]
> 53: gpio_padcfg [0x6e, 53] DW1 [0x00003c6e : 0x00000000 : 0x0000006e]
> 54: gpio_padcfg [0x6e, 54] DW1 [0x00003c6f : 0x00000000 : 0x0000006f]
> 55: gpio_padcfg [0x6e, 55] DW1 [0x00003c70 : 0x00000000 : 0x00000070]
> 58: gpio_padcfg [0x6e, 58] DW0 [0x40000500 : 0x40000100 : 0x40000100]
sd card pins, configured by fsp when scs/sdcard is enabled; I assume they were fixed by CB:34900
> 31: gpio_padcfg [0x6e, 31] DW0 [0x40000700 : 0x40000400 : 0x40000400]
> 33: gpio_padcfg [0x6e, 33] DW0 [0x40000702 : 0x40000400 : 0x40000402]
clkreq; affected pads are B5-B10; if these get overridden, then the clkreq settings in the devicetree mismatch pad config; iow one of both is wrong
> 201: gpio_padcfg [0x6a, 20] DW0 [0x40000500 : 0x40000100 : 0x40000100]
> 202: gpio_padcfg [0x6a, 21] DW0 [0x40100500 : 0x40900100 : 0x40900100]
C20/C21, that's UART2, which is disabled in the dt, which results in SerialIoUartMode[2]=0 and should keep fsp from changing the pads... strange
> 206: gpio_padcfg [0x6a, 25] DW0 [0x40000402 : 0x40000800 : 0x40000802]
That one is set to native when SataPortsInterlockSw[x]=1; however, no board sets it. strange o.O
> 220: gpio_padcfg [0x6a, 39] DW0 [0x40000500 : 0x40000100 : 0x40000100]
> 221: gpio_padcfg [0x6a, 40] DW0 [0x40000500 : 0x40000100 : 0x40000100]
> 223: gpio_padcfg [0x6a, 42] DW0 [0x40000500 : 0x40000100 : 0x40000100]
> 225: gpio_padcfg [0x6a, 44] DW0 [0x40000500 : 0x40000100 : 0x40000100]
> 227: gpio_padcfg [0x6a, 46] DW0 [0x40000500 : 0x40000100 : 0x40000100]
DPPC, HPD, etc. fixed by CB:31520
>
> I have this in notes and internal bugs:
>
> In some cases, FSP is just configuring a GPIO for native mode when the board requires it to be a GPI or GPO. In other cases, the termination is set differently and in some cases no-connect GPIOs are being configured as native functions.
>
> Again from internal bug, I see that this was fixed in FSP or coreboot by adding and initializing required UPDs. Examples:
> https://review.coreboot.org/c/coreboot/+/31520
> https://review.coreboot.org/c/coreboot/+/34900
>
> Eventually, for TGL/JSL, Intel added `GpioOverride` that skips all GPIO configuration in FSP if this UPD is set by coreboot.
Yeah, would be nice to have that for other platforms as well :/
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Change subject: acpi: Add support for reporting CrashLog in BERT table
......................................................................
Patch Set 9:
(4 comments)
Patchset:
PS9:
All comments resolved
File src/arch/x86/acpi_bert_storage.c:
https://review.coreboot.org/c/coreboot/+/49799/comment/83a5d012_4bbe0e3b
PS7, Line 230: 2
> Ack
Done
File src/arch/x86/acpi_bert_storage.c:
https://review.coreboot.org/c/coreboot/+/49799/comment/14a0fbfc_cee188a4
PS8, Line 229: 2
> Is this defined somewhere already? If not, would you mind adding a `#define` for this?
Done
https://review.coreboot.org/c/coreboot/+/49799/comment/12a77ab5_ab96bba5
PS8, Line 229: recort
> record
Done
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Change subject: soc/intel/tigerlake: Add CrashLog implementation for intel TGL
......................................................................
Patch Set 10:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49943/comment/96755780_2d63325c
PS9, Line 7: soc/intel/tigerlake: Add CrashLog implementation for intel TGL.
> Please remove the period/dot at the end of commit message summaries.
Done
https://review.coreboot.org/c/coreboot/+/49943/comment/72c5c41f_9a524dc7
PS9, Line 11: The state of relevant registers is preserved across a warm reset.
> Please add a reference to the specification.
CB:50202
Specs uploaded in CL 50202
https://review.coreboot.org/c/coreboot/+/49943/comment/324d1646_452266d4
PS9, Line 12:
> 1. Why is it SOC specific? […]
1- It is SOC specific because the overall Crashlog architecture is still evolving/changing from SOC to to SOC. It is planned to eventually converge on future SOCs.
2- Documentation added in CB:50202
https://review.coreboot.org/c/coreboot/+/49943/comment/7909f234_66b8b836
PS9, Line 14: TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.
> Please add documentation, or add the utilities and how you called them here.
In addition to the document in CB:50202, plans to open source the crashlog decoder is in the work. Once made public, that utility will come with its own documentation or user guide. This CL is meant to enable the crashLog feature on TGL
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Tim Wawrzynczak, Duncan Laurie, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49943
to look at the new patch set (#10).
Change subject: soc/intel/tigerlake: Add CrashLog implementation for intel TGL
......................................................................
soc/intel/tigerlake: Add CrashLog implementation for intel TGL
CrashLog is a diagnostic feature for Intel TGL based platforms.
It is meant to capture the state of the platform before a crash.
The state of relevant registers is preserved across a warm reset.
BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.
Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com>
Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809
---
M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/acpi.c
A src/soc/intel/tigerlake/crashlog_lib.c
A src/soc/intel/tigerlake/include/soc/crashlog_def.h
A src/soc/intel/tigerlake/include/soc/crashlog_lib.h
M src/soc/intel/tigerlake/include/soc/iomap.h
M src/soc/intel/tigerlake/include/soc/pci_devs.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
11 files changed, 927 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/49943/10
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Change subject: soc/intel/skylake: Set "PEG?Enable" UPD directly
......................................................................
Abandoned
Incorrect and not necessary
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Change subject: soc/intel/skylake: Set "PEG?Enable" UPD directly
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS4:
> I'm still not convinced this patch can really improve much. […]
Initially, the idea was to cleanup the function by avoiding unnecessary configuration. However, if coreboot prefers to guarantee certain settings, rather than using a default, then you're right, it's not necessary.
File src/soc/intel/skylake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/50045/comment/5a873b1c_fe97fc7f
PS4, Line 174: if (dev && dev->enabled) {
> Now this will leave FSP UPDs unprogrammed for disabled PEG RPs. If you want to avoid rewriting the UPD, you have to write the desired values in one statement, and actually remove the write in the if-block:
>
> m_cfg->Peg0Enable = dev && dev->enabled ? 2 : 0;
> if (m_cfg->Peg0Enable) { ...
>
> How many nanoseconds does this shave off the boot time, though?
The difference is definitely within margin of error, but that does look cleaner.
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Change subject: mb/biostar/th61-itx/early_init.c: Clean includes
......................................................................
Patch Set 1: Code-Review+2
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31250 )
Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Furquan, do you remember what pads exactly were overwritten? I'm surprised there was no problem in s […]
I had used this diff:
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index 294218c42f..34d46bfe4d 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -265,10 +265,10 @@ static void gpio_configure_pad(const struct pad_config *cfg)
soc_pad_conf &= mask[i];
soc_pad_conf |= pad_conf & ~mask[i];
- if (IS_ENABLED(CONFIG_DEBUG_GPIO))
+ if (soc_pad_conf != pad_conf)
printk(BIOS_DEBUG,
- "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
- " : 0x%08x]\n",
+ "%d: gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
+ " : 0x%08x]\n", cfg->pad,
comm->port, relative_pad_in_comm(comm, cfg->pad), i,
pad_conf,/* old value */
cfg->pad_config[i],/* value passed from gpio table */
And this was the output I got for hatch:
17: gpio_padcfg [0x6e, 17] DW0 [0x40000600 : 0x40000400 : 0x40000400]
31: gpio_padcfg [0x6e, 31] DW0 [0x40000700 : 0x40000400 : 0x40000400]
33: gpio_padcfg [0x6e, 33] DW0 [0x40000702 : 0x40000400 : 0x40000402]
201: gpio_padcfg [0x6a, 20] DW0 [0x40000500 : 0x40000100 : 0x40000100]
202: gpio_padcfg [0x6a, 21] DW0 [0x40100500 : 0x40900100 : 0x40900100]
206: gpio_padcfg [0x6a, 25] DW0 [0x40000402 : 0x40000800 : 0x40000802]
220: gpio_padcfg [0x6a, 39] DW0 [0x40000500 : 0x40000100 : 0x40000100]
221: gpio_padcfg [0x6a, 40] DW0 [0x40000500 : 0x40000100 : 0x40000100]
223: gpio_padcfg [0x6a, 42] DW0 [0x40000500 : 0x40000100 : 0x40000100]
225: gpio_padcfg [0x6a, 44] DW0 [0x40000500 : 0x40000100 : 0x40000100]
227: gpio_padcfg [0x6a, 46] DW0 [0x40000500 : 0x40000100 : 0x40000100]
51: gpio_padcfg [0x6e, 51] DW1 [0x00003c6c : 0x00000000 : 0x0000006c]
52: gpio_padcfg [0x6e, 52] DW1 [0x00003c6d : 0x00000000 : 0x0000006d]
53: gpio_padcfg [0x6e, 53] DW1 [0x00003c6e : 0x00000000 : 0x0000006e]
54: gpio_padcfg [0x6e, 54] DW1 [0x00003c6f : 0x00000000 : 0x0000006f]
55: gpio_padcfg [0x6e, 55] DW1 [0x00003c70 : 0x00000000 : 0x00000070]
58: gpio_padcfg [0x6e, 58] DW0 [0x40000500 : 0x40000100 : 0x40000100]
I have this in notes and internal bugs:
In some cases, FSP is just configuring a GPIO for native mode when the board requires it to be a GPI or GPO. In other cases, the termination is set differently and in some cases no-connect GPIOs are being configured as native functions.
Again from internal bug, I see that this was fixed in FSP or coreboot by adding and initializing required UPDs. Examples:
https://review.coreboot.org/c/coreboot/+/31520https://review.coreboot.org/c/coreboot/+/34900
Eventually, for TGL/JSL, Intel added `GpioOverride` that skips all GPIO configuration in FSP if this UPD is set by coreboot.
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Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Comment-Date: Mon, 01 Feb 2021 19:33:33 +0000
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