coreboot-gerrit February 2021

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Change in coreboot[master]: [WIP] ACPI: Add acpi_reset_gnvs_for_wake()
by Kyösti Mälkki (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50004 ) Change subject: [WIP] ACPI: Add acpi_reset_gnvs_for_wake() ...................................................................... Patch Set 5: (1 comment) Patchset: PS2: > Probably not pushed for rwview yet, rebase conflicts with acpi-gnvs-framework-2 work. CB:50193 -- To view, visit https://review.coreboot.org/c/coreboot/+/50004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3 Gerrit-Change-Number: 50004 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Feb 2021 23:06:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Raul Rangel, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42685 ) Change subject: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config ...................................................................... Patch Set 9: (2 comments) File src/soc/amd/picasso/uart.c: https://review.coreboot.org/c/coreboot/+/42685/comment/e40c7180_c0fd86b5 PS6, Line 60: Help > D14F0 seems to only be for 1.8MHz and configuring legacy UART IO. […] Ack File src/soc/amd/picasso/uart.c: https://review.coreboot.org/c/coreboot/+/42685/comment/674e43f8_1b3beea5 PS8, Line 106: generator divisor programming? 16*115200 = 1.8432M. */ > AFAICS one cannot currently select AMD_SOC_UART_1_8MZ anyways with psp_verstage since the register w […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/42685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993 Gerrit-Change-Number: 42685 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Feb 2021 22:55:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42685 to look at the new patch set (#9). Change subject: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config ...................................................................... soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config TBD: Actually used for picasso UART. But can it be changed to PCI config write? Looks like PSP-verstage currently has no mapping of this bank. Would be nice if the first code we execute had control over the UART configuration... Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h 2 files changed, 0 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/42685/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/42685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993 Gerrit-Change-Number: 42685 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Kyösti Mälkki has restored this change. ( https://review.coreboot.org/c/coreboot/+/42685 ) Change subject: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/42685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993 Gerrit-Change-Number: 42685 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: restore

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by build bot (Jenkins) (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Duncan Laurie. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49766/comment/1df1f023_60f233fc PS4, Line 70: /* If external phy gating is not implemented, S0i3.3/S0i3.4/S0i2.2 are not recommended. */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 4 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 22:50:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by Shreesh Chhabbi (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Shreesh Chhabbi, Duncan Laurie. Hello build bot (Jenkins), Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Duncan Laurie, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49766 to look at the new patch set (#4). Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates S0i3.2 and S0i3.3 are applicable only if wake on voice is disabled. As per Platform Design Guide, S0i3.2 and S0i3.3 substates need to be disabled for Tigerlake. Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 4 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb,soc/intel: Add wake source fields in GNVS
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Lance Zhao, Angel Pons, Patrick Rudolph. Hello Lance Zhao, build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50193 to look at the new patch set (#2). Change subject: sb,soc/intel: Add wake source fields in GNVS ...................................................................... sb,soc/intel: Add wake source fields in GNVS For the moment, these are most not used but become a necessity for a unified <soc/nvs.h> approach. They would be required for the implementation of _SWS method for OSPM to determine the reason for system waking up. The related hardware registers are present with these platforms. It's expected that ACPI power-management related GNVS entries are grouped together to form a single struct in later works. Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/quark/include/soc/nvs.h M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/include/soc/nvs.h M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/include/soc/nvs.h M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/include/soc/nvs.h M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/include/soc/nvs.h M src/southbridge/intel/ibexpeak/acpi/globalnvs.asl M src/southbridge/intel/ibexpeak/include/soc/nvs.h M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/include/soc/nvs.h 15 files changed, 48 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/50193/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Gerrit-Change-Number: 50193 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common: Use only byte access for old GPIO
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48689 ) Change subject: soc/amd/common: Use only byte access for old GPIO ...................................................................... soc/amd/common: Use only byte access for old GPIO Change-Id: I06ec29845d051d9b90ab6f3cfb269ad5e6b75ea8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h 1 file changed, 0 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/48689/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index ca32f23..4b80a28 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -305,31 +305,11 @@ return read8(acpimmio_gpio_100 + reg); } -static inline uint16_t gpio_100_read16(uint8_t reg) -{ - return read16(acpimmio_gpio_100 + reg); -} - -static inline uint32_t gpio_100_read32(uint8_t reg) -{ - return read32(acpimmio_gpio_100 + reg); -} - static inline void gpio_100_write8(uint8_t reg, uint8_t value) { write8(acpimmio_gpio_100 + reg, value); } -static inline void gpio_100_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_gpio_100 + reg, value); -} - -static inline void gpio_100_write32(uint8_t reg, uint32_t value) -{ - write32(acpimmio_gpio_100 + reg, value); -} - /* New GPIO banks configuration registers */ static inline void *gpio_ctrl_ptr(uint8_t gpio_num) -- To view, visit https://review.coreboot.org/c/coreboot/+/48689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06ec29845d051d9b90ab6f3cfb269ad5e6b75ea8 Gerrit-Change-Number: 48689 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add support for external clock buffer
by Furquan Shaikh (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50162 ) Change subject: soc/intel/alderlake: Add support for external clock buffer ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50162/comment/6a1016f8_a802a8e2 PS1, Line 9: 3 CLKSRC using external clock buffer. : CLKSRC 6 provides feed clock to discrete buffer for further : distribution to platform. This is mainboard specific design and nothing to do with what SoC supports. From SoC standpoint, it supports 7 CLKSRC signals. How those signals are routed on the board is mainboard design. File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/50162/comment/87456af5_0dddfb07 PS1, Line 152: GEN3_EXTERNAL_CLOCK_BUFFER I don't understand why this is a SoC config. It is a mainboard-specific design. File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/50162/comment/5b835319_54437f31 PS1, Line 156: m_cfg->PcieClkSrcUsage[i] = 0; > Did you send me the schematics? Subrata, I do not understand what this change is trying to achieve. There are 7 CLKSRCs on ADL-P. Thus, FSP UPDs need to know how each of these CLKSRCs are routed -- RP, Free running, LAN, etc. Beyond that, a mainboard might choose to distribute any clock source in any way it wants. But, FSP doesn't really care about that because there is nothing in the SoC that needs to be configured for the additional clock sources that are generated by the mainboard. So, why is this code setting PcieClkSrcUsage for something that the FSP doesn't care about? -- To view, visit https://review.coreboot.org/c/coreboot/+/50162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If49d756ed47d577fd839516d4e707563700453d2 Gerrit-Change-Number: 50162 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 22:42:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Add the ASL code
by V Sowmya (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49733 ) Change subject: mb/intel/shadowmountain: Add the ASL code ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49733/comment/0fcde7b5_db5c19ec PS1, Line 9: This patch includes the ASL code for shadowmountain board. > It’s only DSDT? Mention, that you include the common files? Done https://review.coreboot.org/c/coreboot/+/49733/comment/8b65f927_09117a0e PS1, Line 12: TEST= Boot shadowmountain board, dump and verify the ASL entries. > Which entries? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e Gerrit-Change-Number: 49733 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 22:36:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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coreboot-gerrit February 2021