coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

1 participants
7192 discussions

Change in coreboot[master]: soc/intel/alderlake: Add support for external clock buffer
by Subrata Banik (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50162 ) Change subject: soc/intel/alderlake: Add support for external clock buffer ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50162/comment/a0dc0b3a_e0e7eba6 PS1, Line 9: 3 CLKSRC using external clock buffer. : CLKSRC 6 provides feed clock to discrete buffer for further : distribution to platform. > This is mainboard specific design and nothing to do with what SoC supports. […] @Furquan, you can looks into 2 things 1. GetPchMaxPcieClockNum function in FSP source code 2. In ADL-P any schematics that you have (RVP, Pre-CEP, CEP), i believe you will find SRCCLK_OE#7-9 derived from ADL-P PCH. Although i'm yet to connect dots but this is what i understood, FSP is considering 10 CLKSRC for ADL-P and if we make SRCCLK8-9 Not used then its disabling those CLKSRC and device connected to RP8 (x1 slot) is unable to get detected. Hence till the time, i'm further debugging this issue, making sure those CLKSRC are not disable as we have some external device connected there and validation folks are reporting regression File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/50162/comment/a34be4f9_37022690 PS1, Line 156: m_cfg->PcieClkSrcUsage[i] = 0; > Subrata, I do not understand what this change is trying to achieve. […] i have added some answer below -- To view, visit https://review.coreboot.org/c/coreboot/+/50162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If49d756ed47d577fd839516d4e707563700453d2 Gerrit-Change-Number: 50162 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 03:29:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/voxel: Add gpio-keys ACPI node for PENH
by Sheng-Liang Pan (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Nick Vaccaro, YH Lin. Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49967 ) Change subject: mb/google/volteer/var/voxel: Add gpio-keys ACPI node for PENH ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0959df5d0f069048777df81b0d4092ea90314eb Gerrit-Change-Number: 49967 Gerrit-PatchSet: 2 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 03:08:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: hatch: Modify genesis PcieClkSrc settings
by Joe Tessler (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Neill Corlett. Joe Tessler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50101 ) Change subject: hatch: Modify genesis PcieClkSrc settings ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50101/comment/fcc6b4aa_f1e0a2be PS2, Line 9: to work around issue with Longsys SSD > This was required to support a specific SSD module on the M. […] After chatting again with them, I confirmed this new SSD module is a raw PCIe drive (not SATA). Apparently the original settings only supported SATA drives. -- To view, visit https://review.coreboot.org/c/coreboot/+/50101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30c2179be9b9ddd50168a7f35be800e969800e10 Gerrit-Change-Number: 50101 Gerrit-PatchSet: 2 Gerrit-Owner: Neill Corlett <corlett(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Neill Corlett <corlett(a)google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 02:13:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Joe Tessler <jrt(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] Documentation/coding_style: Clarify line limit for text blocks
by Julius Werner (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Nico Huber, Angel Pons, Michael Niewöhner, Werner Zeh. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49542 ) Change subject: [RFC] Documentation/coding_style: Clarify line limit for text blocks ...................................................................... Patch Set 1: (1 comment) File Documentation/coding_style.md: https://review.coreboot.org/c/coreboot/+/49542/comment/135d23af_20e52e8d PS1, Line 97: the overall line length should not exceed 96 chars. > I also can't understand how that makes anything more complicated, for me it's the exact opposite. We use 72 chars in emails, in commit messages, why make an exception for code comments? Just because editors are dull and coders lazy? Kind of, yeah. Emails are easy because most programs (editors, mailers, review software, etc.) can be programmed to automatically break or at least show a border after X characters. I don't know of anything that supports this kind of "characters after indent" thing you want here. And I think in practice that means barely anyone will do it, barely any reviewer will check it, checkpatch isn't gonna find it, and so this rule would just end up adding more confusion and inconsistency. I do a lot more reviewing than coding for this project and I am certainly not going to start counting characters on everyone's patches by hand because Gerrit has no way to make something like this clearly visible. I can't imagine anyone else will, either. At some point reviewer/coder convenience absolutely does become a factor that needs to be weighed against the others. And I don't think we should have a situation where basically nobody ever cares about this except for that one time when someone randomly happens to point it out in your CL and then that paragraph in that patch has to be adjusted while everything else is still line length wild west. -- To view, visit https://review.coreboot.org/c/coreboot/+/49542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12485453721ff01299bba2ade910793f5a032045 Gerrit-Change-Number: 49542 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 02:02:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is sel...
by Johnny Lin (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Jingle Hsu, Angel Pons, Arthur Heymans, Morgan Jang, Patrick Rudolph. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50102 ) Change subject: intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is selected ...................................................................... Patch Set 3: (1 comment) File src/security/intel/txt/Kconfig: https://review.coreboot.org/c/coreboot/+/50102/comment/f66cc74e_7b149895 PS2, Line 9: select TPM_STARTUP_IGNORE_POSTINIT > I suspect this may be specific to Xeon-SP, and possibly causes a regression on Haswell. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49cc3b0077b220b0ca0bfa048be1e3d3d7023b05 Gerrit-Change-Number: 50102 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 01:42:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is sel...
by Johnny Lin (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Jingle Hsu, Arthur Heymans, Morgan Jang. Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Christian Walter, Jingle Hsu, Angel Pons, Arthur Heymans, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50102 to look at the new patch set (#3). Change subject: intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is selected ...................................................................... intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is selected Because ACM already does TPM initialization. Change-Id: I49cc3b0077b220b0ca0bfa048be1e3d3d7023b05 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/50102/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49cc3b0077b220b0ca0bfa048be1e3d3d7023b05 Gerrit-Change-Number: 50102 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src: Remove unused <bootstate.h>
by Johnny Lin (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Morgan Jang, Patrick Rudolph, HAOUAS Elyes. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50203 ) Change subject: src: Remove unused <bootstate.h> ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63 Gerrit-Change-Number: 50203 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 02 Feb 2021 01:36:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ
by Furquan Shaikh (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Subrata Banik. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50130 ) Change subject: soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/50130/comment/8b286601_a2d427a0 PS4, Line 137: CONFIG_MAX_PCIE_CLOCK_REQ This is not correct. The index for PcieClkSrcClkReq is clock source and the value is clock req. Thus, the array still needs to be of size `CONFIG_MAX_PCIE_CLOCK_SRC`. -- To view, visit https://review.coreboot.org/c/coreboot/+/50130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d223c165f819669722cbc80245fa8ec20372352 Gerrit-Change-Number: 50130 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 01:20:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Override SMBIOS type 3 Number Of Power Cords
by Jingle Hsu (Code Review) 02 Feb '21

02 Feb '21

Jingle Hsu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50016 ) Change subject: mb/ocp/deltalake: Override SMBIOS type 3 Number Of Power Cords ...................................................................... Abandoned it defaults to 1 already -- To view, visit https://review.coreboot.org/c/coreboot/+/50016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I582fe8ea147df9a347da66056a739319ac11b4f6 Gerrit-Change-Number: 50016 Gerrit-PatchSet: 1 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/amd/majolica: add fmd sections to build chromeos bootimage
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Mathew King. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50208 ) Change subject: mb/amd/majolica: add fmd sections to build chromeos bootimage ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: i'm a bit conflicted about where this might go, since i try to keep chromebook/vboot specific things out of the AMD reference boards to make sure that no dependencies on chrome-specific functionality lands in the soc code -- To view, visit https://review.coreboot.org/c/coreboot/+/50208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6 Gerrit-Change-Number: 50208 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 00:48:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2021