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Change subject: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
......................................................................
Patch Set 3: Code-Review+1
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Change subject: drivers/generic/bayhub_lv2: Add driver for BayHub lv2
......................................................................
drivers/generic/bayhub_lv2: Add driver for BayHub lv2
Add a driver which puts the device into power-saving mode.
BUG=b:177955523
BRANCH=zork
TEST=boot and see this message:
BayHub LV2: Power-saving enabled 110102
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
Change-Id: Idc1340b1a6fe7063d16c8ea16488d6e2b8b308cc
---
A src/drivers/generic/bayhub_lv2/Kconfig
A src/drivers/generic/bayhub_lv2/Makefile.inc
A src/drivers/generic/bayhub_lv2/chip.h
A src/drivers/generic/bayhub_lv2/lv2.c
A src/drivers/generic/bayhub_lv2/lv2.h
M src/include/device/pci_ids.h
6 files changed, 125 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/49783/8
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Change subject: include/cbfs.h: Add comment for chain-includes of commonlib
......................................................................
include/cbfs.h: Add comment for chain-includes of commonlib
Change-Id: I98fb5df0148a3f5fe0bc5b08c5a0b8b1e95c4624
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/include/cbfs.h
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Change subject: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
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Patch Set 3: Code-Review+1
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Change subject: mb/google/volteer: update thermal table for Eldrid
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Hi Googler, could you help to review the CL? Thanks.
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Change subject: arch/{arm,riscv}/boot.c: Add missing <commonlib/bsd/cbfs_serialized.h>
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50167/comment/95a38d3f_19d7c7e1
PS3, Line 7: arch/{arm,riscv}/boot.c: Add missing <commonlib/bsd/cbfs_serialized.h>
> It isn't missing. People use coreboot headers like <cbfs. […]
I think I definitely have a problem with indirect chain-includes.
I'll add a comment into 'cbfs.h' explaining that it is supposed to chain-include commonlib headers.
In the other hand and maybe out of topic, I feel like this indirect chain-include is complicated. As an example, 'offsetof' should be defined in <stddef.h>, I finely find it at <commonlib/bsd/helpers.h> ( https://review.coreboot.org/c/coreboot/+/44738/4)
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Change subject: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config
......................................................................
Patch Set 9:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/42685/comment/03aec7fb_e1977acc
PS6, Line 7: Drop ACPIMMIO ban
> Why have it if PCI config write does the same thing, with less confusion? If PSP did map this partic […]
Ack
https://review.coreboot.org/c/coreboot/+/42685/comment/b28c686f_a9b46e40
PS6, Line 10: PCI config write
> No PCI config access from psp-verstage?
Ack
File src/soc/amd/picasso/uart.c:
https://review.coreboot.org/c/coreboot/+/42685/comment/f3250b23_f3d03863
PS8, Line 107: if (CONFIG(AMD_SOC_UART_1_8MZ)) {
> if (ENV_X86 && CONFIG(AMD_SOC_UART_1_8MZ))
Ack
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Change subject: soc/amd/picasso/fch.c: Remove unused <acpi/acpi_pm.h>
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> i've added Kyösti as reviewer here so that he's aware of this, so if it might cause an issue he's at […]
Thanks, I currently rebase often as I need to juggle things around and often only postprocess the include lines.
The file probably gets added back sometime in future, I plan to move the power-management related ACPI stuff (acpi_is_wakeup_s3, wake_source, maybe sth else) to <acpi/acpi_pm.h>. To have <acpi/acpi.h> everywhere where none of the ACPI table related functions or structs are needed is s a bit heavy to my liking.
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Change subject: soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI code
......................................................................
Patch Set 1: Code-Review+2
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Hello Hung-Te Lin, build bot (Jenkins), Jason Glenesk, Raul Rangel, Philipp Hug, Marshall Dawson, Julius Werner, ron minnich, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: src: Remove unused <cbfs.h>
......................................................................
src: Remove unused <cbfs.h>
Change-Id: Idc11f1e131df2e01864fedac864bda5e11f2d17b
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/mainboard/google/auron/variants/auron_paine/spd/spd.c
M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
M src/mainboard/google/auron/variants/gandof/spd/spd.c
M src/mainboard/google/auron/variants/lulu/spd/spd.c
M src/mainboard/google/auron/variants/samus/spd/spd.c
M src/mainboard/google/zork/mainboard.c
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
M src/soc/amd/common/block/psp/psp_smm.c
8 files changed, 1 insertion(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/50166/7
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