coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/common: Refactor single GPIO programming
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42691 ) Change subject: soc/amd/common: Refactor single GPIO programming ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa6bd6996fd14dde4b1abcccbd2ae6ef933c87b Gerrit-Change-Number: 42691 Gerrit-PatchSet: 14 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 00:33:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by Shreesh Chhabbi (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Shreesh Chhabbi. Hello build bot (Jenkins), Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Duncan Laurie, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49766 to look at the new patch set (#8). Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates S0i3.2 and S0i3.3 are applicable only if wake on voice is disabled. As per Platform Design Guide, S0i3.2 and S0i3.3 substates need to be disabled for Tigerlake. Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 35 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 8 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by build bot (Jenkins) (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... Patch Set 7: (4 comments) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49766/comment/6cff885a_6876241c PS7, Line 65: //disable_mask |= LPM_S0i3_0 | LPM_S0i3_1 | trailing whitespace https://review.coreboot.org/c/coreboot/+/49766/comment/21386c9e_abf56893 PS7, Line 72: /* If external phy gating is not implemented, trailing whitespace https://review.coreboot.org/c/coreboot/+/49766/comment/cff101a7_2d442c12 PS7, Line 78: if (is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_BT)) || trailing whitespace https://review.coreboot.org/c/coreboot/+/49766/comment/cfc01e17_1343c56b PS7, Line 79: is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI)) || trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 7 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 00:27:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by build bot (Jenkins) (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Shreesh Chhabbi. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... Patch Set 6: (4 comments) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49766/comment/79990e0a_cb705aa2 PS6, Line 65: //disable_mask |= LPM_S0i3_0 | LPM_S0i3_1 | trailing whitespace https://review.coreboot.org/c/coreboot/+/49766/comment/9f88e12c_75346417 PS6, Line 72: /* If external phy gating is not implemented, trailing whitespace https://review.coreboot.org/c/coreboot/+/49766/comment/2dee9185_89f7b51f PS6, Line 78: if (is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_BT)) || trailing whitespace https://review.coreboot.org/c/coreboot/+/49766/comment/ae0ba2e9_4cb460d0 PS6, Line 79: is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI)) || trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 6 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 00:25:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by Shreesh Chhabbi (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh. Hello build bot (Jenkins), Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Duncan Laurie, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49766 to look at the new patch set (#6). Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates S0i3.2 and S0i3.3 are applicable only if wake on voice is disabled. As per Platform Design Guide, S0i3.2 and S0i3.3 substates need to be disabled for Tigerlake. Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 35 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 6 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by Shreesh Chhabbi (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Shreesh Chhabbi. Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... Patch Set 4: (1 comment) This change is ready for review. File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49766/comment/bd0ef2b3_988a4bbe PS3, Line 236: LpmStateEnableMask > I think we can probably do this: […] Hi Furquan, I did not find the upds for external bypass, external clk gate and external phy gate. Are you suggesting to have these read from device tree and check their status to enable/disable substates? -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 4 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 00:21:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: rename sb_init_acpi_ports tofch_init_acpi_ports
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50209 ) Change subject: soc/amd: rename sb_init_acpi_ports tofch_init_acpi_ports ...................................................................... soc/amd: rename sb_init_acpi_ports tofch_init_acpi_ports There's no dedicated south bridge any more and now we have integrated FCHs in the SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d --- M src/soc/amd/picasso/fch.c M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/50209/1 diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index fa99db8..e6cd51a 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -115,7 +115,7 @@ } } -static void sb_init_acpi_ports(void) +static void fch_init_acpi_ports(void) { u32 reg; @@ -220,7 +220,7 @@ void fch_init(void *chip_info) { i2c_soc_init(); - sb_init_acpi_ports(); + fch_init_acpi_ports(); acpi_pm_gpe_add_events_print_events(); gpio_add_events(); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 2a91596..2a78ff9 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -356,7 +356,7 @@ printk(BIOS_DEBUG, "%s\n", __func__); } -static void sb_init_acpi_ports(void) +static void fch_init_acpi_ports(void) { u32 reg; @@ -406,7 +406,7 @@ { struct chipset_power_state *state; - sb_init_acpi_ports(); + fch_init_acpi_ports(); state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); if (state) { -- To view, visit https://review.coreboot.org/c/coreboot/+/50209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d Gerrit-Change-Number: 50209 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/majolica: add fmd sections to build chromeos bootimage
by Mathew King (Code Review) 02 Feb '21

02 Feb '21

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50208 ) Change subject: mb/amd/majolica: add fmd sections to build chromeos bootimage ...................................................................... mb/amd/majolica: add fmd sections to build chromeos bootimage BUG=b:177909472 TEST=builds Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/amd/majolica/board.fmd 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/50208/1 diff --git a/src/mainboard/amd/majolica/board.fmd b/src/mainboard/amd/majolica/board.fmd index 442d80f..90cf2eb 100644 --- a/src/mainboard/amd/majolica/board.fmd +++ b/src/mainboard/amd/majolica/board.fmd @@ -2,6 +2,12 @@ BIOS { EC 128K RW_MRC_CACHE 64K + RW_LEGACY(CBFS) 4K + FW_MAIN_A(CBFS) 1M + VBLOCK_A 8K + FW_MAIN_B(CBFS) 1M + VBLOCK_B 8K + SHARED_DATA 8K FMAP 4K COREBOOT(CBFS) } -- To view, visit https://review.coreboot.org/c/coreboot/+/50208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6 Gerrit-Change-Number: 50208 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI code
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50207 ) Change subject: soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI code ...................................................................... soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI code commit 3f2467032e3e40cd456d2d9fe5120a60283784aa changed this in the APCI code itself, but the change in the ACPI byte code generation in pcie_gpp.c was missed and this patch fixes that. TEST=Fixes the regression on Mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I60de29581296101947336f70343d6206af97e307 --- M src/soc/amd/picasso/pcie_gpp.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/50207/1 diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 3101eb4..00b32a0 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -127,9 +127,9 @@ acpigen_write_method("_PRT", 0); - /* If (PMOD) */ + /* If (PICM) */ acpigen_write_if(); - acpigen_emit_namestring("PMOD"); + acpigen_emit_namestring("PICM"); /* Return (Package{...}) */ acpigen_emit_byte(RETURN_OP); @@ -192,7 +192,7 @@ * * Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table * { - * If (PMOD) + * If (PICM) * { * Return (Package (0x04) * { -- To view, visit https://review.coreboot.org/c/coreboot/+/50207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60de29581296101947336f70343d6206af97e307 Gerrit-Change-Number: 50207 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines
by Raul Rangel (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50205 ) Change subject: soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba Gerrit-Change-Number: 50205 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Feb 2021 23:20:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021