Attention is currently required from: Furquan Shaikh, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi.
Hello build bot (Jenkins), Furquan Shaikh, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Duncan Laurie, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
......................................................................
soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
This change uses the following information to determine the appropriate S0ix
states to enable as per PDG document: 607872 for TGL UP3 UP Rev2p2 (section 10.13):
1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH
In some cases, it is recommended to use a shallower state for S0ix even if the higher
state can be achieved (e.g. with external gating not enabled). This recommendation is
because the shallower state is determined to provide better power savings as per the
above document.
BUG=b:177821896
TEST=Build coreboot for volteer
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com>
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 75 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/28
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Attention is currently required from: Jonathan Zhang, Philipp Deppenwiese, Deomid "rojer" Ryabkov.
Hello build bot (Jenkins), Jonathan Zhang, Philipp Deppenwiese, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: Apply locked MSR check to all BDW-DE platforms
......................................................................
Apply locked MSR check to all BDW-DE platforms
It was initially applied to Wedge100 and MonoLake in CB:30290
and the issue has not been observed on Watson as well.
Original change: [CB:30290]
Signed-off-by: Deomid "rojer" Ryabkov <rojer9(a)fb.com>
Change-Id: Ica9557ff159321abed55f9402aee626f18fe526b
---
M src/mainboard/ocp/monolake/romstage.c
M src/mainboard/ocp/wedge100s/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
3 files changed, 22 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/50307/6
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Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne/chip: add PCI bus scanning
......................................................................
soc/amd/cezanne/chip: add PCI bus scanning
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I76b0eb4470ac4a48e1caeaf507b5e6c45bb88119
---
M src/soc/amd/cezanne/chip.c
1 file changed, 14 insertions(+), 0 deletions(-)
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