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Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
......................................................................
Patch Set 24:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49766/comment/a7679c9c_28b4c8e4
PS9, Line 7: Disable S0i3.2 & S0i3.3 substates
:
: S0i3.2 and S0i3.3 are applicable only if wake on voice is
: disabled. As per Platform Design Guide, S0i3.2 and S0i3.3
: substates need to be disabled for Tigerlake.
> Hi Furquan, what would be the right text to use for commit message?
Probably something like:
soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
This change uses the following information to determine the appropriate S0ix states to enable as per <reference doc/section #>:
1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH
In some cases, it is recommended to use a shallower state for S0ix even if the higher state can be achieved (e.g. with external gating not enabled). This recommendation is because the shallower state is determined to provide better power savings as per the above document.
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Chris Wang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50288
to look at the new patch set (#3).
Change subject: soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
......................................................................
soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527
---
M src/soc/amd/picasso/include/soc/iomap.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/50288/3
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Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )
Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
......................................................................
Patch Set 23:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49766/comment/92c1dc4b_cd7ee1bb
PS9, Line 7: Disable S0i3.2 & S0i3.3 substates
:
: S0i3.2 and S0i3.3 are applicable only if wake on voice is
: disabled. As per Platform Design Guide, S0i3.2 and S0i3.3
: substates need to be disabled for Tigerlake.
> This needs update
Hi Furquan, what would be the right text to use for commit message?
https://review.coreboot.org/c/coreboot/+/49766/comment/b1854959_b459efe0
PS9, Line 12:
> Can you please check what is the lowest power state reported by coreboot and actually observed on vo […]
We see S0i3.2 as the lowest state on all the TGL based devices.
File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/49766/comment/a5ce9b5b_5bc4ba1f
PS9, Line 502: enabled
> Rather than saying "enabled", I think it should say "Mainboard design uses external clock gating" si […]
Ok. Updated it.
https://review.coreboot.org/c/coreboot/+/49766/comment/b3dc7b82_557deed9
PS9, Line 506: ExternalClkGated
> nit: use external_clk_gated instead of ExternalClkGated. […]
I did not know this. Makes sense and its easy to now distinguish between FSP UPDs and Coreboot specific board options.
File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/49766/comment/c2e879b2_3429d4e7
PS9, Line 67: recommended
> It would be good to capture in commit message what "recommended" means i.e. […]
Ok.
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