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Change subject: soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
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Patch Set 3: Code-Review+2
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Change subject: soc/amd/cezanne/pcie_gpp: scan internal PCI buses
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/cezanne/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/50334/comment/5dad21dc_20b3a7f3
PS3, Line 16: 17H
> Do we need a new id?
that id is used in renoir and cezanne and i just used the first family/model name a pci id was used. apart from the core complex renoir and cezanne are pretty much the same. you can re-check what got added in https://review.coreboot.org/c/coreboot/+/47703/5/src/include/device/pci_ids… but i think i double-checked
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Change subject: soc/amd/cezanne/chip: add PCI bus scanning
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Change subject: arch/x86/cpu.c: Remove redundant <arch/cpu.h>
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50304/comment/94652cd4_f8da862f
PS1, Line 8:
> Is it because we chain-include it from a different header? If so, please mention which one.
Done
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Change subject: soc/amd/cezanne/pcie_gpp: scan internal PCI buses
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/cezanne/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/50334/comment/fa5d9317_e40e1fa5
PS3, Line 16: 17H
Do we need a new id?
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Change subject: soc/amd/cezanne/chip: add PCI bus scanning
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Patrick Georgi, Martin Roth, Marshall Dawson,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/amd/cezanne/pcie_gpp: scan internal PCI buses
......................................................................
soc/amd/cezanne/pcie_gpp: scan internal PCI buses
TEST=The devices on the internal buses now get resources assigned.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: If7ff0f2ecde9189691548e071ddcfe1916933571
---
M src/soc/amd/cezanne/Makefile.inc
A src/soc/amd/cezanne/pcie_gpp.c
2 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/50334/3
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Patrick Georgi, Martin Roth, Marshall Dawson,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: [UNTESTED] soc/amd/cezanne/pcie_gpp: scan internal PCI buses
......................................................................
[UNTESTED] soc/amd/cezanne/pcie_gpp: scan internal PCI buses
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: If7ff0f2ecde9189691548e071ddcfe1916933571
---
M src/soc/amd/cezanne/Makefile.inc
A src/soc/amd/cezanne/pcie_gpp.c
2 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/50334/2
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