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Change subject: [UNTESTED] soc/amd/cezanne/pcie_gpp: scan internal PCI buses
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/cezanne/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/50334/comment/9a9929e9_8a7567b2
PS1, Line 24: };
adding a line without newline at end of file
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Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
......................................................................
Patch Set 29:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49766/comment/c43824d4_216e39ea
PS9, Line 7: Disable S0i3.2 & S0i3.3 substates
:
: S0i3.2 and S0i3.3 are applicable only if wake on voice is
: disabled. As per Platform Design Guide, S0i3.2 and S0i3.3
: substates need to be disabled for Tigerlake.
> Probably something like: […]
This looks perfect. Updated the commit msg now.
https://review.coreboot.org/c/coreboot/+/49766/comment/bcc30636_02261229
PS9, Line 12:
> Shouldn't it be S0i3. […]
With this change, testing now Furquan. I was referring to the lowest state reported prior to this change.
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Hello build bot (Jenkins), Furquan Shaikh, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Duncan Laurie, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49766
to look at the new patch set (#29).
Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
......................................................................
soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
This change uses the following information to determine the
appropriate S0ix states to enable as per PDG document: 607872
for TGL UP3 UP Rev2p2 (section 10.13):
1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH
In some cases, it is recommended to use a shallower state for
S0ix even if the higher state can be achieved (e.g. with external
gating not enabled). This recommendation is because the shallower
state is determined to provide better power savings as per the
above document.
BUG=b:177821896
TEST=Build coreboot for volteer
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com>
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 75 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/29
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