coreboot-gerrit February 2021

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Change in coreboot[master]: arch/x86/smbios: Add missing guard
by Raul Rangel (Code Review) 06 Feb '21

06 Feb '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50340 ) Change subject: arch/x86/smbios: Add missing guard ...................................................................... arch/x86/smbios: Add missing guard smbios_type0_bios_version is only defined if HAVE_ACPI_TABLES is set. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I626ab954496833f46d6a785d92cc3b7e7d87e165 --- M src/arch/x86/smbios.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/50340/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index c7827ed..8bc49b1 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -422,7 +422,7 @@ t->vendor = smbios_add_string(t->eos, "coreboot"); t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); - if (CONFIG(CHROMEOS)) { + if (CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES)) { uintptr_t version_address = (uintptr_t)t->eos; /* SMBIOS offsets start at 1 rather than 0 */ version_address += (u32)smbios_string_table_len(t->eos) - 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/50340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I626ab954496833f46d6a785d92cc3b7e7d87e165 Gerrit-Change-Number: 50340 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust
by Martin Roth (Code Review) 05 Feb '21

05 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50240 ) Change subject: soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust ...................................................................... soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust add UPD for RV2 USB3 phy setting adjust. Note: it only for RV2 silicon and not available for RV/PCO. Usb 3.1 PHY Parameters: 1. RX_EQ_DELTA_IQ_OVRD_VAL -Override value for rx_eq_delta_iq. Range 0-0xF 2. RX_EQ_DELTA_IQ_OVRD_EN -Enable override value for rx_eq_delta_iq. Range 0-0x1 3. Override value for rx_vref_ctrl. Range 0 - 0x1F 4. Enable override value for rx_vref_ctrl. Range 0 - 0x1 5. Override value for tx_vboost_lvl: 0 - 0x7. 6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 7. Override value for rx_vref_ctrl. Range 0 - 0x1F 8. Enable override value for rx_vref_ctrl. Range 0 - 0x1 9. Override value for tx_vboost_lvl: 0 - 0x7. 10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 BUG=b:175192931 TEST=Build/verify the valule will been apply on dirinboz Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c M src/vendorcode/amd/fsp/picasso/FspsUpd.h 5 files changed, 143 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index e014ce3..9b0dd9a 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -134,6 +134,47 @@ .tx_res_tune = 0x01, }" + # Start RV2 USB3 PHY Parameters + register "usb3_phy_override" = "0" + + # USB3 Port0 Default + register "usb3_phy_tune_params[0]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port1 Default + register "usb3_phy_tune_params[1]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port2 Default + register "usb3_phy_tune_params[2]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port3 Default + register "usb3_phy_tune_params[3]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # SUP_DIG_LVL_OVRD_IN Default + register "usb3_rx_vref_ctrl" = "0x10" + register "usb3_rx_vref_ctrl_en" = "0x00" + register "usb_3_tx_vboost_lvl" = "0x07" + register "usb_3_tx_vboost_lvl_en" = "0x00" + + # SUPX_DIG_LVL_OVRD_IN Default + register "usb_3_rx_vref_ctrl_x" = "0x10" + register "usb_3_rx_vref_ctrl_en_x" = "0x00" + register "usb_3_tx_vboost_lvl_x" = "0x07" + register "usb_3_tx_vboost_lvl_en_x" = "0x00" + + # End RV2 USB3 phy setting + # USB OC pin mapping register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_1" # USB C1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 5ec9010..a3c4573 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -134,6 +134,47 @@ .tx_res_tune = 0x01, }" + # Start RV2 USB3 PHY Parameters + register "usb3_phy_override" = "0" + + # USB3 Port0 Default + register "usb3_phy_tune_params[0]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port1 Default + register "usb3_phy_tune_params[1]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port2 Default + register "usb3_phy_tune_params[2]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port3 Default + register "usb3_phy_tune_params[3]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # SUP_DIG_LVL_OVRD_IN Default + register "usb3_rx_vref_ctrl" = "0x10" + register "usb3_rx_vref_ctrl_en" = "0x00" + register "usb_3_tx_vboost_lvl" = "0x07" + register "usb_3_tx_vboost_lvl_en" = "0x00" + + # SUPX_DIG_LVL_OVRD_IN Default + register "usb_3_rx_vref_ctrl_x" = "0x10" + register "usb_3_rx_vref_ctrl_en_x" = "0x00" + register "usb_3_tx_vboost_lvl_x" = "0x07" + register "usb_3_tx_vboost_lvl_en_x" = "0x00" + + # End RV2 USB3 phy setting + # SPI Configuration register "common_config.spi_config" = "{ .normal_speed = SPI_SPEED_33M, /* MHz */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 9a7d2a5..313b6c3 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -66,6 +66,13 @@ }; #define USB_PORT_COUNT 6 + +struct __packed usb3_phy_tune { + uint8_t rx_eq_delta_iq_ovrd_val; + uint8_t rx_eq_delta_iq_ovrd_en; +}; +/* the RV2 USB3 port count */ +#define RV2_USB3_PORT_COUNT 4 #define USB_PD_PORT_COUNT 2 enum sd_emmc_driver_strength { @@ -247,6 +254,30 @@ USB_OC_NONE = 0xf, } usb_port_overcurrent_pin[USB_PORT_COUNT]; + /* RV2 SOC Usb 3.1 PHY Parameters */ + uint8_t usb3_phy_override; + /* + * 1,RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF + * 2,RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1 + */ + struct usb3_phy_tune usb3_phy_tune_params[RV2_USB3_PORT_COUNT]; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F */ + uint8_t usb3_rx_vref_ctrl; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1 */ + uint8_t usb3_rx_vref_ctrl_en; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1 */ + uint8_t usb_3_tx_vboost_lvl_en; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F.*/ + uint8_t usb_3_rx_vref_ctrl_x; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1. */ + uint8_t usb_3_rx_vref_ctrl_en_x; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl_x; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1. */ + uint8_t usb_3_tx_vboost_lvl_en_x; + /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index df5e1e6..e77cbde 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -5,6 +5,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/platform_descriptors.h> +#include <soc/soc_util.h> #include <fsp/api.h> #include "chip.h" @@ -126,6 +127,23 @@ scfg->xhci_oc_pin_select |= (cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4); } + + if ((get_silicon_type() == SILICON_RV2) && cfg->usb3_phy_override) { + scfg->usb_3_phy_enable = cfg->usb3_phy_override; + for (i = 0; i < FSPS_UPD_RV2_USB3_PORT_COUNT; i++) { + memcpy(scfg->usb_3_port_phy_tune[i], + &cfg->usb3_phy_tune_params[i], + sizeof(scfg->usb_3_port_phy_tune[0])); + } + scfg->usb_3_rx_vref_ctrl = cfg->usb3_rx_vref_ctrl; + scfg->usb_3_rx_vref_ctrl_en = cfg->usb3_rx_vref_ctrl_en; + scfg->usb_3_tx_vboost_lvl = cfg->usb_3_tx_vboost_lvl; + scfg->usb_3_tx_vboost_lvl_en = cfg->usb_3_tx_vboost_lvl_en; + scfg->usb_3_rx_vref_ctrl_x = cfg->usb_3_rx_vref_ctrl_x; + scfg->usb_3_rx_vref_ctrl_en_x = cfg->usb_3_rx_vref_ctrl_en_x; + scfg->usb_3_tx_vboost_lvl_x = cfg->usb_3_tx_vboost_lvl_x; + scfg->usb_3_tx_vboost_lvl_en_x = cfg->usb_3_tx_vboost_lvl_en_x; + } } static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg) diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index aac6fdb..f931bf0 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -12,6 +12,7 @@ #define FSPS_UPD_DXIO_DESCRIPTOR_COUNT 8 #define FSPS_UPD_DDI_DESCRIPTOR_COUNT 4 #define FSPS_UPD_USB2_PORT_COUNT 6 +#define FSPS_UPD_RV2_USB3_PORT_COUNT 4 typedef struct __packed { /** Offset 0x0020**/ uint32_t emmc0_mode; @@ -54,7 +55,17 @@ /** Offset 0x0139**/ uint8_t pwron_varybl_to_blon; /** Offset 0x013A**/ uint8_t pwrdown_bloff_to_varybloff; /** Offset 0x013B**/ uint8_t min_allowed_bl_level; - /** Offset 0x013C**/ uint8_t UnusedUpdSpace0[20]; + /** Offset 0x013C**/ uint8_t usb_3_phy_enable; + /** Offset 0x013D**/ uint8_t usb_3_port_phy_tune[FSPS_UPD_RV2_USB3_PORT_COUNT][2]; + /** Offset 0x0145**/ uint8_t usb_3_rx_vref_ctrl; + /** Offset 0x0146**/ uint8_t usb_3_rx_vref_ctrl_en; + /** Offset 0x0147**/ uint8_t usb_3_tx_vboost_lvl; + /** Offset 0x0148**/ uint8_t usb_3_tx_vboost_lvl_en; + /** Offset 0x0149**/ uint8_t usb_3_rx_vref_ctrl_x; + /** Offset 0x014A**/ uint8_t usb_3_rx_vref_ctrl_en_x; + /** Offset 0x014B**/ uint8_t usb_3_tx_vboost_lvl_x; + /** Offset 0x014C**/ uint8_t usb_3_tx_vboost_lvl_en_x; + /** Offset 0x014D**/ uint8_t UnusedUpdSpace0[3]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/50240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Gerrit-Change-Number: 50240 Gerrit-PatchSet: 14 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/romstage: Store early dram region
by Felix Held (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50338 ) Change subject: soc/amd/cezanne/romstage: Store early dram region ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5 Gerrit-Change-Number: 50338 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 23:30:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Move memmap_early_dram to common blocks
by Felix Held (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50337 ) Change subject: soc/amd/picasso: Move memmap_early_dram to common blocks ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0800c662bb473eb571c74e76a8247298f534b53f Gerrit-Change-Number: 50337 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 23:30:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add root_complex
by build bot (Jenkins) (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50339 ) Change subject: soc/amd/cezanne: Add root_complex ...................................................................... Patch Set 1: (5 comments) File src/soc/amd/cezanne/root_complex.c: https://review.coreboot.org/c/coreboot/+/50339/comment/75413e11_31db1519 PS1, Line 35: * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 line over 96 characters https://review.coreboot.org/c/coreboot/+/50339/comment/73da4abd_fc5989cc PS1, Line 38: * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE line over 96 characters https://review.coreboot.org/c/coreboot/+/50339/comment/25c9f753_6cae1052 PS1, Line 43: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 line over 96 characters https://review.coreboot.org/c/coreboot/+/50339/comment/9aa26f49_78bb29f8 PS1, Line 45: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE line over 96 characters https://review.coreboot.org/c/coreboot/+/50339/comment/55082c1a_c7480ff1 PS1, Line 48: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/50339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Gerrit-Change-Number: 50339 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Feb 2021 23:30:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add chain-include list of headers
by Julius Werner (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: HAOUAS Elyes. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50286 ) Change subject: Documentation: Add chain-include list of headers ...................................................................... Patch Set 4: (2 comments) File Documentation/chain-include.md: https://review.coreboot.org/c/coreboot/+/50286/comment/fa9a956c_d19b3d69 PS4, Line 5: boot You're generally inconsistent what you consider as toplevel directory. If you want to write `include/cbfs.h`, you also have to write `include/boot/coreboot_tables.h` here. I would recommend just always using the <cbfs.h> / <commonlib/cbfs.h> notation and write all files the same way they would appear in an actual #include directive. https://review.coreboot.org/c/coreboot/+/50286/comment/7ecca028_29977553 PS4, Line 43: metadata_hash include/ ? -- To view, visit https://review.coreboot.org/c/coreboot/+/50286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I474d0d4bd660b62c24508bc3eba67154e820d8a4 Gerrit-Change-Number: 50286 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 05 Feb 2021 23:29:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/Makefile.inc: Fix indentation
by Felix Held (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50336 ) Change subject: soc/amd/cezanne/Makefile.inc: Fix indentation ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: uh oh, i really need to tell my IDE not to do that sort of things... -- To view, visit https://review.coreboot.org/c/coreboot/+/50336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id617e98db5b0895071ee98265f68f6106058bd63 Gerrit-Change-Number: 50336 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 23:27:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: Use Kconfig SPI speed & read mode in devicetree
by Felix Held (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50285 ) Change subject: mb/google/zork: Use Kconfig SPI speed & read mode in devicetree ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb: https://review.coreboot.org/c/coreboot/+/50285/comment/ff973812_85296846 PS1, Line 151: .read_mode = CONFIG_EFS_SPI_READ_MODE, is it intended that this changes the mode from 122 to 112? -- To view, visit https://review.coreboot.org/c/coreboot/+/50285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I116adf4fe0de5a2790894618ccff8ebf629fab34 Gerrit-Change-Number: 50285 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 23:25:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add root_complex
by Raul Rangel (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50339 ) Change subject: soc/amd/cezanne: Add root_complex ...................................................................... soc/amd/cezanne: Add root_complex This is a copy/paste of picasso with a few things removed. With this change we can jump into depthcharge. Allocated resources: PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 21c0000 size cde40000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base 100000000 size 30e340000 align 0 gran 0 limit 0 flags e0004200 index 6 PCI: 00:00.0 resource base 40e340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 7 PCI: 00:00.0 resource base 40f000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base 410000000 size 20000000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base cfffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base ceffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b TEST=Boot majolica and see depthcharge finally loading: Starting depthcharge on MAJOLICA... new_rt5682_codec: chip = 0x1A Looking for NVMe Controller 0x3004cac8 @ 00:01:07 src/drivers/flash/memmapped.c:63 flash_setup(): No MMAP windows for SPI flash! Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e --- M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/root_complex.c 2 files changed, 142 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/50339/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 7f59ef4..0e25f63 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += gpio.c ramstage-y += pcie_gpp.c ramstage-y += reset.c +ramstage-y += root_complex.c ramstage-y += uart.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c new file mode 100644 index 0000000..7b349fb --- /dev/null +++ b/src/soc/amd/cezanne/root_complex.c @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/memmap.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <fsp/util.h> +#include <stdint.h> + +/* + * + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (86KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (64KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +static void read_resources(struct device *dev) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + unsigned int idx = 0; + const struct hob_header *hob = fsp_get_hob_list(); + const struct hob_resource *res; + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_resource(dev, idx++, 0, 0xa0000 / KiB); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); + + /* 1MB - bottom of DRAM reserved for early coreboot usage */ + ram_resource(dev, idx++, (1 * MiB) / KiB, + (early_reserved_dram_start - (1 * MiB)) / KiB); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB, + (early_reserved_dram_end - early_reserved_dram_start) / KiB); + + /* top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. */ + ram_resource(dev, idx++, early_reserved_dram_end / KiB, + (mem_usable - early_reserved_dram_end) / KiB); + + mmconf_resource(dev, MMIO_CONF_BASE); + + if (!hob) { + printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + __func__); + return; + } + + for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { + + if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) + continue; + + res = fsp_hob_header_to_resource(hob); + + if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable) + continue; /* 0 through low usable was set above */ + if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO) + continue; /* Done separately */ + + if (res->type == EFI_RESOURCE_SYSTEM_MEMORY) + ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); + else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) + reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); + else + printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + res->type); + } +} + +static struct device_operations root_complex_operations = { + .read_resources = read_resources, + .set_resources = noop_set_resources, + .enable_resources = pci_dev_enable_resources, +}; + +static const struct pci_driver family17_root_complex __pci_driver = { + .ops = &root_complex_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/50339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Gerrit-Change-Number: 50339 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/romstage: Store early dram region
by Raul Rangel (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50338 ) Change subject: soc/amd/cezanne/romstage: Store early dram region ...................................................................... soc/amd/cezanne/romstage: Store early dram region Needed so we can reserve the memory Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5 --- M src/soc/amd/cezanne/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/50338/1 diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index c7e7e5c..773c6a9 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <amdblocks/memmap.h> #include <arch/cpu.h> #include <console/console.h> #include <console/uart.h> @@ -33,5 +34,7 @@ fsp_memory_init(acpi_is_wakeup_s3()); + memmap_stash_early_dram_usage(); + run_ramstage(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/50338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5 Gerrit-Change-Number: 50338 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021