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Change subject: intel/stm: Place resource list right below MSEG
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
This is a prerequisite for the smm_module_loaderv2, which is used by broadwell_de in the last patch.
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Change subject: cpu/x86/smm: Add overflow check
......................................................................
Patch Set 1:
(1 comment)
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PS1:
This is a prerequisite for the smm_module_loaderv2, which is used by broadwell_de in the last patch.
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Change subject: cpu/x86/smm: Add smm_size to relocatable smmstub
......................................................................
Patch Set 1:
(1 comment)
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This is a prerequisite for the smm_module_loaderv2, which is used by broadwell_de in the last patch.
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Change subject: security/intel/stm: Check for processor STM support
......................................................................
Patch Set 1:
(1 comment)
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This is a prerequisite for the smm_module_loaderv2, which is used by broadwell_de in the last patch.
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Change subject: security/intel/stm: Add STM support
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
This is a prerequisite for the smm_module_loaderv2, which is used by broadwell_de in the last patch.
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Change subject: soc/amd/cezanne: Add verstage support
......................................................................
soc/amd/cezanne: Add verstage support
We don't currently support VBOOT_STARTS_BEFORE_BOOTBLOCK. This sets up
verstage to run after bootblock. The offsets are the same as picasso.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/50342/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 611260d..a631870 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -106,10 +106,35 @@
help
The amount of coreboot-allocated heap and stack usage by the FSP.
+config VERSTAGE_ADDR
+ hex
+ depends on VBOOT_SEPARATE_VERSTAGE
+ default 0x2140000
+ help
+ Sets the address in DRAM where verstage should be loaded if running
+ as a separate stage on x86.
+
+config VERSTAGE_SIZE
+ hex
+ depends on VBOOT_SEPARATE_VERSTAGE
+ default 0x80000
+ help
+ Sets the size of DRAM allocation for verstage in linker script if
+ running as a separate stage on x86.
+
+config VBOOT
+ select VBOOT_STARTS_IN_BOOTBLOCK
+ select VBOOT_SEPARATE_VERSTAGE
+
config RAMBASE
hex
default 0x10000000
+config RO_REGION_ONLY
+ string
+ depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
+ default "apu/amdfw"
+
config CPU_ADDR_BITS
int
default 48
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