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Change in coreboot[master]: soc/amd,intel: Drop s3_resume parameter on FSP functions
by Kyösti Mälkki (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Mariusz Szafrański, Lee Leahy, Marshall Dawson, Suresh Bellampalli, Vanessa Eusebio, Huang Jin, Michal Motyl, Andrey Petrov, Patrick Rudolph, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50360 ) Change subject: soc/amd,intel: Drop s3_resume parameter on FSP functions ...................................................................... soc/amd,intel: Drop s3_resume parameter on FSP functions ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp1_1/include/fsp/ramstage.h M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/silicon_init.c M src/soc/amd/cezanne/chip.c M src/soc/amd/picasso/chip.c M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/chip.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/quark/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c 25 files changed, 29 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/50360/1 diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index dec2393..d1b803e 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -8,7 +8,6 @@ /* Perform Intel silicon init. */ void intel_silicon_init(void); -void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup); /* Called after the silicon init code has run. */ void soc_after_silicon_init(void); /* Initialize UPD data before SiliconInit call. */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 34eec6e..22d4f1c 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -51,7 +51,7 @@ } } -void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) +static void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header) { FSP_SILICON_INIT fsp_silicon_init; SILICON_INIT_UPD *original_params; @@ -179,7 +179,7 @@ void intel_silicon_init(void) { fsp_load(); - fsp_run_silicon_init(fsp_get_fih(), acpi_is_wakeup_s3()); + fsp_run_silicon_init(fsp_get_fih()); } /* Initialize the UPD parameters for SiliconInit */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index f8742b7..59d1a4b 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -33,7 +33,7 @@ /* Main FSP stages */ void fsp_memory_init(bool s3wake); -void fsp_silicon_init(bool s3wake); +void fsp_silicon_init(void); void fsp_temp_ram_exit(void); /* @@ -41,7 +41,7 @@ * separately from calling silicon init. It might be required in cases where * stage cache is no longer available by the point SoC calls into silicon init. */ -void fsps_load(bool s3wake); +void fsps_load(void); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index f8e884b..d88d39a 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -191,7 +191,7 @@ return 0; } -void fsps_load(bool s3wake) +void fsps_load(void) { struct fsp_load_descriptor fspld = { .fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_S_CBFS), @@ -220,8 +220,8 @@ load_done = 1; } -void fsp_silicon_init(bool s3wake) +void fsp_silicon_init(void) { - fsps_load(s3wake); + fsps_load(); do_silicon_init(&fsps_hdr); } diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 4a39024..486e40d 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi.h> #include <device/device.h> #include <fsp/api.h> #include <soc/southbridge.h> @@ -13,7 +12,7 @@ static void soc_init(void *chip_info) { - fsp_silicon_init(acpi_is_wakeup_s3()); + fsp_silicon_init(); fch_init(chip_info); } diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 17c7bd5..8722d57 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -102,7 +101,7 @@ { default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; - fsp_silicon_init(acpi_is_wakeup_s3()); + fsp_silicon_init(); data_fabric_set_mmio_np(); fch_init(chip_info); diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index c7e3fb8..95ad865 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -10,7 +10,6 @@ #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/xdci.h> -#include <romstage_handoff.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> @@ -134,7 +133,7 @@ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* Perform silicon specific init. */ - fsp_silicon_init(romstage_handoff_is_resume()); + fsp_silicon_init(); /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob(); diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 9fab277..32f5ea2 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -19,7 +19,6 @@ #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> -#include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -27,7 +26,7 @@ static void soc_fsp_load(void) { - fsps_load(romstage_handoff_is_resume()); + fsps_load(); } static void configure_misc(void) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 7970d66..e21ae39 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -22,7 +22,6 @@ #include <intelblocks/gpio.h> #include <intelblocks/itss.h> #include <intelblocks/pmclib.h> -#include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/heci.h> #include <soc/intel/common/vbt.h> @@ -301,7 +300,7 @@ */ gpi_clear_int_cfg(); - fsp_silicon_init(romstage_handoff_is_resume()); + fsp_silicon_init(); /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 0ae170b..a071337 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -24,7 +24,6 @@ #include <intelblocks/msr.h> #include <intelblocks/sgx.h> #include <reg_script.h> -#include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -140,7 +139,7 @@ static void pre_mp_init(void) { if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) { - fsps_load(romstage_handoff_is_resume()); + fsps_load(); return; } x86_setup_mtrrs_with_detect(); diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0958aac..4f467a1 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -10,7 +10,6 @@ #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/xdci.h> -#include <romstage_handoff.h> #include <soc/intel/common/vbt.h> #include <soc/gpio.h> #include <soc/pci_devs.h> @@ -171,7 +170,7 @@ void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ - fsp_silicon_init(romstage_handoff_is_resume()); + fsp_silicon_init(); /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob(); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index f4b72ab..6a4f773 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -10,7 +10,6 @@ #include <cpu/intel/turbo.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> -#include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -23,7 +22,7 @@ static void soc_fsp_load(void) { - fsps_load(romstage_handoff_is_resume()); + fsps_load(); } static void configure_misc(void) diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 9cf3bfb..77ad8e7 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -43,7 +43,7 @@ static void soc_init(void *data) { - fsp_silicon_init(false); + fsp_silicon_init(); soc_save_dimm_info(); } diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index 359aa11..001a6e1 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -10,7 +10,6 @@ #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/xdci.h> -#include <romstage_handoff.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> @@ -122,7 +121,7 @@ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* Perform silicon specific init. */ - fsp_silicon_init(romstage_handoff_is_resume()); + fsp_silicon_init(); /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob(); diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index d0fa019..984f7f2 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -13,7 +13,6 @@ #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> -#include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -21,7 +20,7 @@ static void soc_fsp_load(void) { - fsps_load(romstage_handoff_is_resume()); + fsps_load(); } static void configure_misc(void) diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index d493f81..134d7cf 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -9,7 +9,6 @@ #include <intelblocks/gpio.h> #include <intelblocks/itss.h> #include <intelblocks/xdci.h> -#include <romstage_handoff.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> @@ -112,7 +111,7 @@ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* Perform silicon specific init. */ - fsp_silicon_init(romstage_handoff_is_resume()); + fsp_silicon_init(); /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob(); diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 1734ba6..dd70c85 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -13,7 +13,6 @@ #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> -#include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -21,7 +20,7 @@ static void soc_fsp_load(void) { - fsps_load(romstage_handoff_is_resume()); + fsps_load(); } static void configure_misc(void) diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index 1f58f84..ce4004d 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -10,7 +10,6 @@ #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/xdci.h> -#include <romstage_handoff.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> @@ -128,7 +127,7 @@ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* Perform silicon specific init. */ - fsp_silicon_init(romstage_handoff_is_resume()); + fsp_silicon_init(); /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob(); diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 6518945..a3790e1 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -13,7 +13,6 @@ #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> -#include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -21,7 +20,7 @@ static void soc_fsp_load(void) { - fsps_load(romstage_handoff_is_resume()); + fsps_load(); } static void configure_misc(void) diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 33033a9..e613ced 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -2,7 +2,6 @@ #include <assert.h> #include <device/device.h> -#include <romstage_handoff.h> #include <soc/ramstage.h> #include <soc/reg_access.h> @@ -103,7 +102,7 @@ | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); /* Perform silicon specific init. */ - fsp_silicon_init(romstage_handoff_is_resume()); + fsp_silicon_init(); } static struct device_operations pci_domain_ops = { diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 1022bfe..fb4a816 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -17,7 +17,6 @@ #include <intelblocks/xdci.h> #include <intelblocks/p2sb.h> #include <intelpch/lockdown.h> -#include <romstage_handoff.h> #include <soc/acpi.h> #include <soc/intel/common/vbt.h> #include <soc/interrupt.h> @@ -55,7 +54,7 @@ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* Perform silicon specific init. */ - fsp_silicon_init(romstage_handoff_is_resume()); + fsp_silicon_init(); /* * Keep the P2SB device visible so it and the other devices are @@ -76,7 +75,7 @@ void soc_fsp_load(void) { - fsps_load(romstage_handoff_is_resume()); + fsps_load(); } static struct device_operations pci_domain_ops = { diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index f07cc58..8be04b6 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -11,7 +11,6 @@ #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/xdci.h> -#include <romstage_handoff.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> @@ -134,7 +133,7 @@ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* Perform silicon specific init. */ - fsp_silicon_init(romstage_handoff_is_resume()); + fsp_silicon_init(); /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob(); diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 36dfa1b..974401f 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -19,7 +19,6 @@ #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> -#include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -27,7 +26,7 @@ static void soc_fsp_load(void) { - fsps_load(romstage_handoff_is_resume()); + fsps_load(); } static void configure_misc(void) diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 778d277..2c731da 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -91,7 +91,7 @@ static void chip_init(void *data) { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); - fsp_silicon_init(false); + fsp_silicon_init(); override_hpet_ioapic_bdf(); pch_enable_ioapic(); pch_lock_dmictl(); diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 4d50a25..92f2afa 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -59,7 +59,7 @@ static void soc_init(void *data) { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); - fsp_silicon_init(false); + fsp_silicon_init(); override_hpet_ioapic_bdf(); pch_lock_dmictl(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/50360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Gerrit-Change-Number: 50360 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/fsp1_1,fsp2_0: Refactor logo display
by Kyösti Mälkki (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Martin Roth, Frans Hendriks, Lee Leahy, Huang Jin, Andrey Petrov, Patrick Rudolph, Wim Vervoorn. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50359 ) Change subject: intel/fsp1_1,fsp2_0: Refactor logo display ...................................................................... intel/fsp1_1,fsp2_0: Refactor logo display Hide the detail of allocation from cbmem from the FSP. Loading of a BMP logo file from CBFS is not tied to FSP version and we do not need two copies of the code, move it under lib/. Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp1_1/Makefile.inc M src/drivers/intel/fsp1_1/include/fsp/ramstage.h D src/drivers/intel/fsp1_1/logo.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc M src/drivers/intel/fsp2_0/include/fsp/api.h D src/drivers/intel/fsp2_0/logo.c M src/drivers/intel/fsp2_0/silicon_init.c M src/include/bootsplash.h M src/lib/Makefile.inc A src/lib/bmp_logo.c M src/mainboard/facebook/fbg1701/board_verified_boot.c M src/soc/intel/apollolake/chip.c M src/soc/intel/braswell/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/skylake/chip.c 18 files changed, 60 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/50359/1 diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index d2cfa53..3ab9096 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -78,7 +78,7 @@ help Selected by platforms that implement their own CAR setup. -config FSP1_1_DISPLAY_LOGO +config BMP_LOGO bool "Enable logo" default n help @@ -87,7 +87,7 @@ config FSP1_1_LOGO_FILE_NAME string "Logo file" - depends on FSP1_1_DISPLAY_LOGO + depends on BMP_LOGO default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp" endif #PLATFORM_USES_FSP1_1 diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index b5dd3c3..4259237 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -21,7 +21,6 @@ ramstage-y += fsp_relocate.c ramstage-y += fsp_util.c ramstage-y += hob.c -ramstage-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.c ramstage-y += ramstage.c ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c ramstage-$(CONFIG_MMA) += mma_core.c @@ -44,7 +43,7 @@ endif # Add logo to the cbfs image -cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp +cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME)) logo.bmp-type := raw logo.bmp-compression := LZMA diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index 50e3bd6..dec2393 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -9,7 +9,6 @@ /* Perform Intel silicon init. */ void intel_silicon_init(void); void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup); -const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size); /* Called after the silicon init code has run. */ void soc_after_silicon_init(void); /* Initialize UPD data before SiliconInit call. */ @@ -17,7 +16,6 @@ void mainboard_silicon_init_params(SILICON_INIT_UPD *params); void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new); -const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params); void load_vbt(SILICON_INIT_UPD *params); #endif /* _INTEL_COMMON_RAMSTAGE_H_ */ diff --git a/src/drivers/intel/fsp1_1/logo.c b/src/drivers/intel/fsp1_1/logo.c deleted file mode 100644 index bcaf157..0000000 --- a/src/drivers/intel/fsp1_1/logo.c +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cbfs.h> -#include <cbmem.h> -#include <soc/ramstage.h> - -const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size) -{ - const struct cbmem_entry *logo_entry = NULL; - void *logo_buffer; - - logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB); - if (logo_entry) { - logo_buffer = cbmem_entry_start(logo_entry); - if (logo_buffer) { - *logo_size = cbfs_load("logo.bmp", (void *)logo_buffer, - 1 * MiB); - if (*logo_size) - *logo_ptr = (UINT32)logo_buffer; - } - } - return (logo_entry); -} diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index ddfc3c7..34eec6e 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootmode.h> +#include <bootsplash.h> #include <acpi/acpi.h> #include <console/console.h> #include <fsp/ramstage.h> @@ -58,7 +59,6 @@ EFI_STATUS status; UPD_DATA_REGION *upd_ptr; VPD_DATA_REGION *vpd_ptr; - const struct cbmem_entry *logo_entry = NULL; /* Display the FSP header */ if (fsp_info_header == NULL) { @@ -85,8 +85,9 @@ load_vbt(&silicon_init_params); mainboard_silicon_init_params(&silicon_init_params); - if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup) - logo_entry = soc_load_logo(&silicon_init_params); + if (CONFIG(BMP_LOGO)) + bmp_load_logo(&silicon_init_params.PcdLogoPtr, + &silicon_init_params.PcdLogoSize); /* Display the UPD data */ if (CONFIG(DISPLAY_UPD_DATA)) @@ -106,8 +107,8 @@ printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); /* The logo_entry can be freed up now as it is not required any longer */ - if (logo_entry && !is_s3_wakeup) - cbmem_entry_remove(logo_entry); + if (CONFIG(BMP_LOGO)) + bmp_release_logo(); /* Mark graphics init done after SiliconInit if VBT was provided */ #if CONFIG(RUN_FSP_GOP) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 285bedf..63394dd 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -184,7 +184,7 @@ bool default n -config FSP2_0_DISPLAY_LOGO +config BMP_LOGO bool "Enable logo" default n depends on HAVE_FSP_LOGO_SUPPORT @@ -195,7 +195,7 @@ config FSP2_0_LOGO_FILE_NAME string "Logo file" - depends on FSP2_0_DISPLAY_LOGO + depends on BMP_LOGO default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp" config FSP_COMPRESS_FSP_S_LZMA diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 0943080..92f6711 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -22,7 +22,6 @@ ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c -ramstage-$(CONFIG_FSP2_0_DISPLAY_LOGO) += logo.c ramstage-y += notify.c ramstage-y += silicon_init.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c @@ -86,7 +85,7 @@ endif # Add logo to the cbfs image -cbfs-files-$(CONFIG_FSP2_0_DISPLAY_LOGO) += logo.bmp +cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP2_0_LOGO_FILE_NAME)) logo.bmp-type := raw logo.bmp-compression := LZMA diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 97e2fea..f8742b7 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -59,16 +59,11 @@ uint8_t fsp_memory_mainboard_version(void); uint8_t fsp_memory_soc_version(void); -/* Load logo to be displayed by FSP */ -const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size); - /* Callback after processing FSP notify */ void platform_fsp_notify_status(enum fsp_notify_phase phase); /* Initialize memory margin analysis settings. */ void setup_mma(FSP_M_CONFIG *memory_cfg); -/* Update the SOC specific logo param and load the logo. */ -const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd); /* Update the SOC specific memory config param for mma. */ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg); diff --git a/src/drivers/intel/fsp2_0/logo.c b/src/drivers/intel/fsp2_0/logo.c deleted file mode 100644 index 314616b..0000000 --- a/src/drivers/intel/fsp2_0/logo.c +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cbfs.h> -#include <cbmem.h> -#include <fsp/api.h> - -const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size) -{ - const struct cbmem_entry *logo_entry = NULL; - void *logo_buffer; - - logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB); - if (logo_entry) { - logo_buffer = cbmem_entry_start(logo_entry); - if (logo_buffer) { - *logo_size = cbfs_load("logo.bmp", (void *)logo_buffer, - 1 * MiB); - if (*logo_size) - *logo_ptr = (UINT32)logo_buffer; - } - } - return (logo_entry); -} diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 8572b24..f8e884b 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <bootsplash.h> #include <cbfs.h> #include <cbmem.h> #include <commonlib/fsp.h> @@ -81,7 +82,6 @@ FSPS_UPD *upd, *supd; fsp_silicon_init_fn silicon_init; uint32_t status; - const struct cbmem_entry *logo_entry = NULL; fsp_multi_phase_si_init_fn multi_phase_si_init; struct fsp_multi_phase_params multi_phase_params; struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number; @@ -106,8 +106,8 @@ platform_fsp_silicon_init_params_cb(upd); /* Populate logo related entries */ - if (CONFIG(FSP2_0_DISPLAY_LOGO)) - logo_entry = soc_load_logo(upd); + if (CONFIG(BMP_LOGO)) + bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); /* Call SiliconInit */ silicon_init = (void *) (uintptr_t)(hdr->image_base + @@ -127,8 +127,8 @@ timestamp_add_now(TS_FSP_SILICON_INIT_END); post_code(POST_FSP_SILICON_EXIT); - if (logo_entry) - cbmem_entry_remove(logo_entry); + if (CONFIG(BMP_LOGO)) + bmp_release_logo(); fsp_debug_after_silicon_init(status); fsps_return_value_handler(FSP_SILICON_INIT_API, status); @@ -225,9 +225,3 @@ fsps_load(s3wake); do_silicon_init(&fsps_hdr); } - -/* Load bmp and set FSP parameters, fsp_load_logo can be used */ -__weak const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd) -{ - return NULL; -} diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h index d5aecf8..10da5aa 100644 --- a/src/include/bootsplash.h +++ b/src/include/bootsplash.h @@ -14,4 +14,8 @@ void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution, unsigned int y_resolution, unsigned int fb_resolution); + +void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size); +void bmp_release_logo(void); + #endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8424cbf..074cb2a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -139,6 +139,7 @@ ramstage-y += hexstrtobin.c ramstage-y += wrdd.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c +ramstage-$(CONFIG_BMP_LOGO) += bmp_logo.c ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c new file mode 100644 index 0000000..330ed6f --- /dev/null +++ b/src/lib/bmp_logo.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <bootsplash.h> +#include <cbfs.h> +#include <cbmem.h> +#include <stdint.h> + +static const struct cbmem_entry *logo_entry; + +void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size) +{ + void *logo_buffer; + + /* CBMEM is locked for S3 resume path. */ + if (acpi_is_wakeup_s3()) + return; + + logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB); + if (!logo_entry) + return; + + logo_buffer = cbmem_entry_start(logo_entry); + if (!logo_buffer) + return; + + *logo_size = cbfs_load("logo.bmp", logo_buffer, 1 * MiB); + if (*logo_size) + *logo_ptr = (uintptr_t)logo_buffer; +} + +void bmp_release_logo(void) +{ + if (logo_entry) + cbmem_entry_remove(logo_entry); + logo_entry = NULL; +} diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index a03c6fc..5fbcf2c 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -57,7 +57,7 @@ static const verify_item_t ram_stage_additional_list[] = { { VERIFY_FILE, OP_ROM_VBT, { { NULL, CBFS_TYPE_RAW } }, HASH_IDX_OPROM, MBOOT_PCR_INDEX_2 }, -#if CONFIG(FSP1_1_DISPLAY_LOGO) +#if CONFIG(BMP_LOGO) { VERIFY_FILE, "logo.bmp", { { NULL, CBFS_TYPE_RAW } }, HASH_IDX_LOGO, MBOOT_PCR_INDEX_2 }, #endif diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 9670a31..7970d66 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -849,10 +849,4 @@ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } -/* Handle FSP logo params */ -const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd) -{ - return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); -} - BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index d759602..407ee2d 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -138,11 +138,6 @@ board_silicon_USB2_override(params); } -const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params) -{ - return fsp_load_logo(&params->PcdLogoPtr, &params->PcdLogoSize); -} - void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) { /* Display the parameters for SiliconInit */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 075c328..d78d426 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -587,9 +587,3 @@ *size = ARRAY_SIZE(serial_io_dev); return serial_io_dev; } - -/* Handle FSP logo params */ -const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd) -{ - return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); -} diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 5b05dd2..1022bfe 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -444,9 +444,3 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* Handle FSP logo params */ -const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd) -{ - return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/50359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04 Gerrit-Change-Number: 50359 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel: Guard TRAP method in ASL
by Kyösti Mälkki (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50358 ) Change subject: soc/intel: Guard TRAP method in ASL ...................................................................... soc/intel: Guard TRAP method in ASL Needed to support build with ACPI_SOC_NVS=n as SMIF object inside GNVS disappears then. Change-Id: Ib798187c24996b74d6345080f7d48c3f657eb512 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/common/acpi/platform.asl 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/50358/1 diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index b1dda02..342a4ef 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -17,6 +17,7 @@ DBG0, 8 } +#if CONFIG(ACPI_SOC_NVS) /* SMI I/O Trap */ Method(TRAP, 1, Serialized) { @@ -24,6 +25,7 @@ TRP0 = 0 // Generate trap Return (SMIF) // Return value of SMI handler } +#endif /* ACPI_SOC_NVS */ /* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. -- To view, visit https://review.coreboot.org/c/coreboot/+/50358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib798187c24996b74d6345080f7d48c3f657eb512 Gerrit-Change-Number: 50358 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mainboards: Drop PWRS from GNVS
by Kyösti Mälkki (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Angel Pons, Andrey Petrov, Patrick Rudolph, Lance Zhao, Jason Glenesk, Damien Zammit, Marshall Dawson, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Alexander Couzens, Felix Held. Hello build bot (Jenkins), Raul Rangel, Mariusz Szafrański, Angel Pons, Andrey Petrov, Patrick Rudolph, Lance Zhao, Jason Glenesk, Damien Zammit, Marshall Dawson, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Alexander Couzens, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49352 to look at the new patch set (#9). Change subject: mainboards: Drop PWRS from GNVS ...................................................................... mainboards: Drop PWRS from GNVS Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/dsdt_top.asl M src/mainboard/acer/g43t-am3/acpi_tables.c D src/mainboard/asrock/g41c-gs/acpi_tables.c M src/mainboard/asus/p5qc/acpi_tables.c M src/mainboard/asus/p5ql-em/acpi_tables.c D src/mainboard/asus/p5qpl-am/acpi_tables.c D src/mainboard/foxconn/g41s-k/acpi_tables.c M src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c M src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl D src/mainboard/intel/dg41wv/acpi_tables.c M src/mainboard/intel/dg43gt/acpi_tables.c M src/mainboard/lenovo/g505s/acpi/mainboard.asl D src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/amd/stoneyridge/include/soc/nvs.h M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/pch/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/denverton_ns/include/soc/nvs.h M src/soc/intel/quark/include/soc/nvs.h M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/include/soc/nvs.h M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/include/soc/nvs.h M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/include/soc/nvs.h M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/include/soc/nvs.h M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/include/soc/nvs.h M src/southbridge/intel/ibexpeak/acpi/globalnvs.asl M src/southbridge/intel/ibexpeak/include/soc/nvs.h M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/include/soc/nvs.h 44 files changed, 34 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/49352/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/49352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Gerrit-Change-Number: 49352 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Drop CID1 from GNVS
by Kyösti Mälkki (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Lance Zhao, Furquan Shaikh, Subrata Banik, Kyösti Mälkki, Patrick Rudolph. Hello Lance Zhao, build bot (Jenkins), Furquan Shaikh, Angel Pons, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50297 to look at the new patch set (#2). Change subject: soc/intel: Drop CID1 from GNVS ...................................................................... soc/intel: Drop CID1 from GNVS The only reference to CID1 is in common/acpi/wifi.asl and only two braswell boards include it. Everywhere else the value in GNVS was unused. Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c 11 files changed, 4 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/50297/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba Gerrit-Change-Number: 50297 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/broadwell: Drop `SPIBARx` macros
by Angel Pons (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Nico Huber, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50042 ) Change subject: soc/intel/broadwell: Drop `SPIBARx` macros ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > The current situation is a mess, I known. But I'm not sure […] Hmmm, most other Intel southbridges do not use SPIBARx() macros. I'll think about it while I deduplicate other stuff. -- To view, visit https://review.coreboot.org/c/coreboot/+/50042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cd91fec92e33dbb7dfebbfd440e3db2e9b4e914 Gerrit-Change-Number: 50042 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 06 Feb 2021 16:16:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/broadwell: Drop `SPIBARx` macros
by Nico Huber (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Angel Pons, Arthur Heymans, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50042 ) Change subject: soc/intel/broadwell: Drop `SPIBARx` macros ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: The current situation is a mess, I known. But I'm not sure if this doesn't make it worse. Intel has (almost?) always documented the SPIBAR separately, even if its location was implicitly configured relative to RCBA. Also, newer chipsets have a separate BAR now (with mostly identical registers). So it would seem much more future-proof to have SPIBAR macros or functions. -- To view, visit https://review.coreboot.org/c/coreboot/+/50042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cd91fec92e33dbb7dfebbfd440e3db2e9b4e914 Gerrit-Change-Number: 50042 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 06 Feb 2021 16:05:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/broadwell: Use southbridge common RCBA
by Nico Huber (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Angel Pons, Arthur Heymans, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50041 ) Change subject: soc/intel/broadwell: Use southbridge common RCBA ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94953bed3f331848271464bee829f8209167f150 Gerrit-Change-Number: 50041 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 06 Feb 2021 15:53:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: update USB 3 controller phy Parameter for dirinboz
by Kevin Chiu (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Kevin Chiu, Martin Roth, Furquan Shaikh, Bhanu Prakash Maiya, Felix Held. Hello build bot (Jenkins), Martin Roth, Furquan Shaikh, Patrick Georgi, Kangheui Won, Bhanu Prakash Maiya, Eric Peers, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50282 to look at the new patch set (#5). Change subject: mb/google/zork: update USB 3 controller phy Parameter for dirinboz ...................................................................... mb/google/zork: update USB 3 controller phy Parameter for dirinboz Recommendation from SOC to config IQ=8 for U3 port0, vboost for all U3 ports for passing ESD pin test. BUG=b:175192931 BRANCH=zork TEST=1. emerge-zork coreboot 2. run U3 SI/ESD pin test => pass Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/50282/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/50282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f Gerrit-Change-Number: 50282 Gerrit-PatchSet: 5 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/x4x/raminit: Fix Clock Enable on DDR3
by Arthur Heymans (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Damien Zammit, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50353 ) Change subject: nb/intel/x4x/raminit: Fix Clock Enable on DDR3 ...................................................................... Patch Set 3: (1 comment) File src/northbridge/intel/x4x/raminit_ddr23.c: https://review.coreboot.org/c/coreboot/+/50353/comment/71395a31_395570ef PS3, Line 779: * clock for all ranks. > nb/intel/i945 has the `OVERRIDE_CLOCK_DISABLE` Kconfig option, maybe add it to x4x as well? We know other x4x boards work well with DDR3 (various G41 boards, and the Acer G43T-AM3). Sounds good. -- To view, visit https://review.coreboot.org/c/coreboot/+/50353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1eb77ed2d2b563fb3b92ca33b900f7d1dbc85fe Gerrit-Change-Number: 50353 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 06 Feb 2021 15:13:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2021