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Change subject: nb/intel/x4x: Drop commented-out statement
......................................................................
Patch Set 1:
(1 comment)
File src/northbridge/intel/x4x/raminit_ddr23.c:
https://review.coreboot.org/c/coreboot/+/49389/comment/20153c26_26c2de23
PS1, Line 775: MCHBAR8_AND(0x400 * i + 0x5a0 + 3,
: ~rank2clken[r + i * 4]);
> > I do remember that I needed this to have all clock signals enabled for a (DDR3) board to work (bet […]
Alright, I added comments on that patch.
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Change subject: nb/intel/x4x/raminit: Fix Clock Enable on DDR3
......................................................................
Patch Set 3:
(1 comment)
File src/northbridge/intel/x4x/raminit_ddr23.c:
https://review.coreboot.org/c/coreboot/+/50353/comment/55cb5b7c_89ccb902
PS3, Line 779: * clock for all ranks.
nb/intel/i945 has the `OVERRIDE_CLOCK_DISABLE` Kconfig option, maybe add it to x4x as well? We know other x4x boards work well with DDR3 (various G41 boards, and the Acer G43T-AM3).
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Change subject: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
......................................................................
Patch Set 4:
(1 comment)
File src/northbridge/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/49749/comment/03f683b4_0b869fcf
PS4, Line 64: EPBAR64
> Is the reason for keeping those here, that older Intel NB don't have any EP/DMI 64bit registers?
I kept these here because other northbridges don't use them, and I'm not sure if 64-bit register accesses would work properly on all northbridges (I know they work on Haswell, but no idea about others).
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Hello build bot (Jenkins), Nico Huber, Damien Zammit, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50356
to look at the new patch set (#2).
Change subject: nb/intel/pineview: Rewrite hex values in lowercase
......................................................................
nb/intel/pineview: Rewrite hex values in lowercase
Most hex values are already lowercase. For consistency reasons, rewrite
uppercase hex values in lowercase.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I185b448ca7822fa89c57efe788e05b582b259c37
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/northbridge/intel/pineview/mchbar_regs.h
M src/northbridge/intel/pineview/raminit.c
2 files changed, 314 insertions(+), 314 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/50356/2
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Change subject: nb/intel/pineview: Delete rude and useless comment
......................................................................
Patch Set 1: Code-Review+2
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Change subject: nb/intel/pineview: Clean up FIXMEs in raminit
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Patch Set 1: Code-Review+2
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Change subject: Revert "util/lint: Add test for documentation in util dirs"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Just pushed to share my local solution to be able
to commit again. There's likely a better way.
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Change subject: nb/intel/pineview: Delete rude and useless comment
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Patch Set 1: Code-Review+2
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