coreboot-gerrit February 2021

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Change in coreboot[master]: sb/intel/*/Kconfig: Order options selections alphabetically
by HAOUAS Elyes (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50363 to look at the new patch set (#4). Change subject: sb/intel/*/Kconfig: Order options selections alphabetically ...................................................................... sb/intel/*/Kconfig: Order options selections alphabetically Also add "config SOUTH_BRIDGE_OPTIONS". Change-Id: I6ae6e2a893372e124a6594852e436c18e30b36e1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 8 files changed, 112 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/50363/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ae6e2a893372e124a6594852e436c18e30b36e1 Gerrit-Change-Number: 50363 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: print i2c3 timing reg
by build bot (Jenkins) (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: Hung-Te Lin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50366 ) Change subject: WIP: soc/mediatek/mt8192: print i2c3 timing reg ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/common/i2c.c: https://review.coreboot.org/c/coreboot/+/50366/comment/27bd74ea_be3cf240 PS1, Line 194: printk(BIOS_ERR, "[mtk_debug][i2c%d][addr0x%x] ext_conf(0x%x)\n", bus, addr, read32(&regs->ext_conf)); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/50366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee6a1e47e7387ecdb7fde999f8bcdaecf03f9f31 Gerrit-Change-Number: 50366 Gerrit-PatchSet: 1 Gerrit-Owner: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Sun, 07 Feb 2021 09:05:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: print i2c3 timing reg
by Jg Daolongzhu (Code Review) 07 Feb '21

07 Feb '21

Jg Daolongzhu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50366 ) Change subject: WIP: soc/mediatek/mt8192: print i2c3 timing reg ...................................................................... WIP: soc/mediatek/mt8192: print i2c3 timing reg as title TEST=Boots correctly on MT8192P1 Signed-off-by: jg_daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Change-Id: Iee6a1e47e7387ecdb7fde999f8bcdaecf03f9f31 --- M src/soc/mediatek/common/i2c.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/50366/1 diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c old mode 100644 new mode 100755 index 3c54b17..7fb883d --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -191,6 +191,10 @@ write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG); write32(&dma_regs->dma_en, I2C_DMA_START_EN); + printk(BIOS_ERR, "[mtk_debug][i2c%d][addr0x%x] ext_conf(0x%x)\n", bus, addr, read32(&regs->ext_conf)); +printk(BIOS_ERR, "[mtk_debug] timing(0x%x)\n", read32(&regs->timing)); +printk(BIOS_ERR, "[mtk_debug]ltiming(0x%x)\n", read32(&regs->ltiming)); +printk(BIOS_ERR, "[mtk_debug]clock_div(0x%x)\n", read32(&regs->clock_div)); /* start transfer transaction */ write32(&regs->start, 0x1); -- To view, visit https://review.coreboot.org/c/coreboot/+/50366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee6a1e47e7387ecdb7fde999f8bcdaecf03f9f31 Gerrit-Change-Number: 50366 Gerrit-PatchSet: 1 Gerrit-Owner: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Update gpio config and device tree fo...
by zanxi chen (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: Martin Roth, Henry Sun, Tao Xia. zanxi chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50262 ) Change subject: mb/google/dedede/var/sasukette: Update gpio config and device tree for sasukette ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b73c660a304fa64d7cc9bf2df050d4e5a5c36fc Gerrit-Change-Number: 50262 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-CC: Jessie Xu <xuyanan(a)huaqin.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Sun, 07 Feb 2021 08:43:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: test of crashlog moved to common code
by Francois Toguo Fotso (Code Review) 07 Feb '21

07 Feb '21

Francois Toguo Fotso has removed Lijian Zhao from this change. ( https://review.coreboot.org/c/coreboot/+/50364 ) Change subject: test of crashlog moved to common code ...................................................................... Removed reviewer Lijian Zhao. -- To view, visit https://review.coreboot.org/c/coreboot/+/50364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92cd009494cf135a82cee7ca0c42fac30b96eb6e Gerrit-Change-Number: 50364 Gerrit-PatchSet: 1 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: sb/intel/common/Kconfig: Hide intel related options
by HAOUAS Elyes (Code Review) 07 Feb '21

07 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50365 ) Change subject: sb/intel/common/Kconfig: Hide intel related options ...................................................................... sb/intel/common/Kconfig: Hide intel related options Change-Id: I860641e4023f26434fef452271fde71e12232f73 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/common/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/50365/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 1bdefd4..00a92e0 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -1,3 +1,9 @@ +if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || \ + SOUTHBRIDGE_INTEL_I82371EB || SOUTHBRIDGE_INTEL_I82801DX || \ + SOUTHBRIDGE_INTEL_I82801GX || SOUTHBRIDGE_INTEL_I82801IX || \ + SOUTHBRIDGE_INTEL_I82801JX || SOUTHBRIDGE_INTEL_I82870 || \ + SOUTHBRIDGE_INTEL_IBEXPEAK || SOUTHBRIDGE_INTEL_LYNXPOINT + config SOUTHBRIDGE_INTEL_COMMON_RESET def_bool n select HAVE_CF9_RESET @@ -116,3 +122,5 @@ hex depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS default 0x400 + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/50365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I860641e4023f26434fef452271fde71e12232f73 Gerrit-Change-Number: 50365 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/*/Kconfig: Order options selections alphabetically
by HAOUAS Elyes (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50363 to look at the new patch set (#3). Change subject: sb/intel/*/Kconfig: Order options selections alphabetically ...................................................................... sb/intel/*/Kconfig: Order options selections alphabetically Also add "config SOUTH_BRIDGE_OPTIONS". Change-Id: I6ae6e2a893372e124a6594852e436c18e30b36e1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 8 files changed, 112 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/50363/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ae6e2a893372e124a6594852e436c18e30b36e1 Gerrit-Change-Number: 50363 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/*/Kconfig: Order options selections alphabetically
by HAOUAS Elyes (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: Patrick Rudolph, HAOUAS Elyes. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50363 to look at the new patch set (#2). Change subject: sb/intel/*/Kconfig: Order options selections alphabetically ...................................................................... sb/intel/*/Kconfig: Order options selections alphabetically Change-Id: I6ae6e2a893372e124a6594852e436c18e30b36e1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 8 files changed, 84 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/50363/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ae6e2a893372e124a6594852e436c18e30b36e1 Gerrit-Change-Number: 50363 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/*/Kconfig: Order options selections alphabetically
by HAOUAS Elyes (Code Review) 07 Feb '21

07 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50363 ) Change subject: sb/intel/*/Kconfig: Order options selections alphabetically ...................................................................... sb/intel/*/Kconfig: Order options selections alphabetically Change-Id: I6ae6e2a893372e124a6594852e436c18e30b36e1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 8 files changed, 85 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/50363/1 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index e3ad885..bed209c 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -13,29 +13,29 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT - select SOUTHBRIDGE_INTEL_COMMON_FINALIZE - select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 - select SOUTHBRIDGE_INTEL_COMMON_PMCLIB - select SOUTHBRIDGE_INTEL_COMMON_PMBASE - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_RESET - select IOAPIC - select HAVE_USBDEBUG_OPTIONS + select HAVE_INTEL_CHIPSET_LOCKDOWN select HAVE_SMI_HANDLER - select USE_WATCHDOG_ON_BOOT + select HAVE_USBDEBUG_OPTIONS + select INTEL_DESCRIPTOR_MODE_CAPABLE + select IOAPIC select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK - select INTEL_DESCRIPTOR_MODE_CAPABLE - select SOUTHBRIDGE_INTEL_COMMON_GPIO select RTC - select HAVE_INTEL_CHIPSET_LOCKDOWN - select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT - select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_FINALIZE + select SOUTHBRIDGE_INTEL_COMMON_GPIO + select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select USE_WATCHDOG_ON_BOOT config EHCI_BAR hex diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index d0eec0e..f20ac11 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -1,6 +1,7 @@ config SOUTHBRIDGE_INTEL_I82371EB - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_RESET bool + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 840aeb4..2e99173 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -3,15 +3,15 @@ config SOUTHBRIDGE_INTEL_I82801DX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select IOAPIC - select HAVE_SMI_HANDLER - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_RESET - select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select HAVE_SMI_HANDLER + select IOAPIC + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG if SOUTHBRIDGE_INTEL_I82801DX diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index c880793..8d05eb4 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -5,24 +5,24 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT - select IOAPIC - select USE_WATCHDOG_ON_BOOT - select HAVE_SMI_HANDLER - select SOUTHBRIDGE_INTEL_COMMON_GPIO - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 if BOOT_DEVICE_SPI_FLASH - select SOUTHBRIDGE_INTEL_COMMON_PMCLIB - select SOUTHBRIDGE_INTEL_COMMON_PMBASE select HAVE_INTEL_CHIPSET_LOCKDOWN - select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select HAVE_SMI_HANDLER select INTEL_HAS_TOP_SWAP - select SOUTHBRIDGE_INTEL_COMMON_SMM - select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_RESET - select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select IOAPIC + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_HPET + select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 if BOOT_DEVICE_SPI_FLASH + select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select USE_WATCHDOG_ON_BOOT if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 3ee2943..5438244 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -9,6 +9,7 @@ select HAVE_USBDEBUG_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select IOAPIC + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB @@ -16,7 +17,6 @@ select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SMM if !NO_SMM select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index bd553ee..7823175 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -11,6 +11,7 @@ select HAVE_USBDEBUG_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select IOAPIC + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB @@ -18,7 +19,6 @@ select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 34ae2f1..ee8c100 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -10,29 +10,29 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT - select IOAPIC - select HAVE_SMI_HANDLER - select USE_WATCHDOG_ON_BOOT - select PCIEXP_ASPM - select PCIEXP_COMMON_CLOCK - select SOUTHBRIDGE_INTEL_COMMON_FINALIZE - select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 - select SOUTHBRIDGE_INTEL_COMMON_SMM - select SOUTHBRIDGE_INTEL_COMMON_PMCLIB - select SOUTHBRIDGE_INTEL_COMMON_PMBASE - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_RESET - select HAVE_USBDEBUG_OPTIONS - select INTEL_DESCRIPTOR_MODE_CAPABLE - select SOUTHBRIDGE_INTEL_COMMON_GPIO select HAVE_INTEL_CHIPSET_LOCKDOWN select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select HAVE_SMI_HANDLER + select HAVE_USBDEBUG_OPTIONS + select INTEL_DESCRIPTOR_MODE_CAPABLE + select IOAPIC + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_FINALIZE + select SOUTHBRIDGE_INTEL_COMMON_GPIO + select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select USE_WATCHDOG_ON_BOOT config EHCI_BAR hex diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index a9a2f5b..7bf5e27 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -10,31 +10,31 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 - select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT - select SOUTHBRIDGE_INTEL_COMMON_FINALIZE - select SOUTHBRIDGE_INTEL_COMMON_PMCLIB - select SOUTHBRIDGE_INTEL_COMMON_PMBASE - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_RESET - select IOAPIC - select HAVE_SMI_HANDLER - select HAVE_USBDEBUG_OPTIONS - select USE_WATCHDOG_ON_BOOT - select PCIEXP_ASPM - select PCIEXP_COMMON_CLOCK - select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT - select RTC - select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP - select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select HAVE_INTEL_CHIPSET_LOCKDOWN select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select HAVE_SMI_HANDLER + select HAVE_USBDEBUG_OPTIONS + select INTEL_DESCRIPTOR_MODE_CAPABLE + select IOAPIC + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + select RTC + select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_FINALIZE + select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP + select SOUTHBRIDGE_INTEL_COMMON_PMBASE + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select USE_WATCHDOG_ON_BOOT config INTEL_LYNXPOINT_LP bool -- To view, visit https://review.coreboot.org/c/coreboot/+/50363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ae6e2a893372e124a6594852e436c18e30b36e1 Gerrit-Change-Number: 50363 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel: Extract `set_global_reset` function
by Angel Pons (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Nico Huber, Martin Roth, Arthur Heymans, Evgeny Zinoviev, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50362 ) Change subject: sb/intel: Extract `set_global_reset` function ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I just tested this with #37115 on a corebooted MacBook Pro 10,1, everything works as expected. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/50362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64c59a01ca153770481c28ae404a5dfe8c5382d2 Gerrit-Change-Number: 50362 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 06 Feb 2021 23:06:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: comment

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coreboot-gerrit February 2021