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Change subject: sb/intel/lynxpoint/acpi/gpio.asl: Convert to ASL 2.0
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
File src/southbridge/intel/lynxpoint/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/50329/comment/62f3d0a0_9a390388
PS1, Line 80: 48
> Since this is a register offset, it makes more sense to keep it in hex.
Done
https://review.coreboot.org/c/coreboot/+/50329/comment/39302737_96abe717
PS1, Line 96: 256
> Same here
Done
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Change subject: soc/amd/cezanne: Add verstage support
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Patch Set 1: Code-Review+1
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Change subject: soc/amd/cezanne: Add root_complex
......................................................................
Patch Set 1:
(3 comments)
File src/soc/amd/cezanne/root_complex.c:
https://review.coreboot.org/c/coreboot/+/50339/comment/4aa97bf0_e6e74c44
PS1, Line 23: reserved_dram_end
To avoid having so much empty space on the left margin, how about moving this to the right side?
https://review.coreboot.org/c/coreboot/+/50339/comment/ea8d2c39_5b5566ab
PS1, Line 88: 1MB
nit: MiB
https://review.coreboot.org/c/coreboot/+/50339/comment/8206460c_2732ae3b
PS1, Line 97: *
nit: remove this `*` to comply with the coding style
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