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Change subject: soc/amd/cezanne/romstage: Store early dram region
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Patch Set 1: Code-Review+2
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Commit Message:
https://review.coreboot.org/c/coreboot/+/50338/comment/72b0764d_e4bf7096
PS1, Line 9: Needed so we can reserve the memory
nit: missing a period at the end of the sentence
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Change subject: soc/amd/picasso: Move memmap_early_dram to common blocks
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Patch Set 1: Code-Review+2
(1 comment)
File src/soc/amd/common/block/include/amdblocks/memmap.h:
https://review.coreboot.org/c/coreboot/+/50337/comment/6bdece40_a3088d4f
PS1, Line 13: uint32_t size;
I wonder if these should be `uintptr_t base` and `size_t size`
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Change subject: soc/amd/cezanne/pcie_gpp: scan internal PCI buses
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Patch Set 3: Code-Review+2
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Change subject: soc/intel/braswell,skylake: Drop logo parameters from devicetree
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Patch Set 1: Code-Review+1
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