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Change in coreboot[master]: payloads: Force sub-make runs for in-tree payloads
by Nico Huber (Code Review) 07 Feb '21

07 Feb '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47638 ) Change subject: payloads: Force sub-make runs for in-tree payloads ...................................................................... payloads: Force sub-make runs for in-tree payloads The sub-process calls break make's dependency tracking, hence we have to always perform the calls if we want to allow automatic, incremental builds. Change-Id: I1bc2406db371e8dddbfdf71f68a6665a5b558f5e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/Makefile.inc 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47638/1 diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc index ec42143..d89b5ba 100644 --- a/payloads/Makefile.inc +++ b/payloads/Makefile.inc @@ -29,12 +29,14 @@ payloads/external/LinuxBoot \ payloads/external/Yabits \ +force-payload: + payloads/coreinfo/build/coreinfo.elf coreinfo: export CCACHE := $(CCACHE) -payloads/coreinfo/build/coreinfo.elf coreinfo: +payloads/coreinfo/build/coreinfo.elf coreinfo: force-payload $(MAKE) -C payloads/coreinfo defaultbuild payloads/nvramcui/build/nvramcui.elf nvramcui: export CCACHE := $(CCACHE) -payloads/nvramcui/build/nvramcui.elf nvramcui: +payloads/nvramcui/build/nvramcui.elf nvramcui: force-payload $(MAKE) -C payloads/nvramcui clean-payloads: @@ -46,4 +48,5 @@ print-repo-info-payloads: -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads nvramcui coreinfo +.PHONY: force-payload coreinfo nvramcui +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads -- To view, visit https://review.coreboot.org/c/coreboot/+/47638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bc2406db371e8dddbfdf71f68a6665a5b558f5e Gerrit-Change-Number: 47638 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: payloads: Pass $(CCACHE) on to in-tree payloads
by Nico Huber (Code Review) 07 Feb '21

07 Feb '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47637 ) Change subject: payloads: Pass $(CCACHE) on to in-tree payloads ...................................................................... payloads: Pass $(CCACHE) on to in-tree payloads Change-Id: Ie15aec4059fbeb99f714c3d674df5fabdb7c081c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/47637/1 diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc index a8c0772..ec42143 100644 --- a/payloads/Makefile.inc +++ b/payloads/Makefile.inc @@ -29,9 +29,11 @@ payloads/external/LinuxBoot \ payloads/external/Yabits \ +payloads/coreinfo/build/coreinfo.elf coreinfo: export CCACHE := $(CCACHE) payloads/coreinfo/build/coreinfo.elf coreinfo: $(MAKE) -C payloads/coreinfo defaultbuild +payloads/nvramcui/build/nvramcui.elf nvramcui: export CCACHE := $(CCACHE) payloads/nvramcui/build/nvramcui.elf nvramcui: $(MAKE) -C payloads/nvramcui -- To view, visit https://review.coreboot.org/c/coreboot/+/47637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie15aec4059fbeb99f714c3d674df5fabdb7c081c Gerrit-Change-Number: 47637 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: nvramcui: Use libpayload's new `Makefile.payload`
by Nico Huber (Code Review) 07 Feb '21

07 Feb '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47636 ) Change subject: nvramcui: Use libpayload's new `Makefile.payload` ...................................................................... nvramcui: Use libpayload's new `Makefile.payload` Change-Id: I34bf659c1a069ccc27ca613bbf86780d4da49259 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/Makefile.inc M payloads/nvramcui/.gitignore M payloads/nvramcui/Makefile 3 files changed, 7 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47636/1 diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc index 79e7748..a8c0772 100644 --- a/payloads/Makefile.inc +++ b/payloads/Makefile.inc @@ -10,7 +10,7 @@ img/coreinfo-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG) cbfs-files-$(CONFIG_NVRAMCUI_SECONDARY_PAYLOAD) += img/nvramcui -img/nvramcui-file := payloads/nvramcui/nvramcui.elf +img/nvramcui-file := payloads/nvramcui/build/nvramcui.elf img/nvramcui-type := payload img/nvramcui-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG) @@ -32,7 +32,7 @@ payloads/coreinfo/build/coreinfo.elf coreinfo: $(MAKE) -C payloads/coreinfo defaultbuild -payloads/nvramcui/nvramcui.elf nvramcui: +payloads/nvramcui/build/nvramcui.elf nvramcui: $(MAKE) -C payloads/nvramcui clean-payloads: diff --git a/payloads/nvramcui/.gitignore b/payloads/nvramcui/.gitignore index 4885853..19a985b 100644 --- a/payloads/nvramcui/.gitignore +++ b/payloads/nvramcui/.gitignore @@ -1,2 +1,2 @@ -build libpayload +.lp.config* diff --git a/payloads/nvramcui/Makefile b/payloads/nvramcui/Makefile index 269d558..c2c15a7 100644 --- a/payloads/nvramcui/Makefile +++ b/payloads/nvramcui/Makefile @@ -1,34 +1,4 @@ -LIBPAYLOAD_DIR=$(CURDIR)/libpayload -XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile -# build libpayload and put .config file in $(CURDIR) instead of ../libpayload -# to avoid pollute the libpayload source directory and possible conflicts -LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config" -CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib - -all: nvramcui.elf - -$(LIBPAYLOAD_DIR): - $(MAKE) -C ../libpayload $(LPOPTS) defconfig - $(MAKE) -C ../libpayload $(LPOPTS) - $(MAKE) -C ../libpayload $(LPOPTS) install - -ifneq ($(strip $(wildcard libpayload)),) -include $(XCOMPILE) -LPGCC = CC="$(GCC_CC_x86_32)" "$(LIBPAYLOAD_DIR)/bin/lpgcc" -%.elf: %.c Makefile - $(LPGCC) $(CFLAGS) -o $*.elf $*.c -else -# If libpayload is not found, first build libpayload, -# then do the make, this time it'll find libpayload -# and generate the nvramcui.elf target -%.elf: $(LIBPAYLOAD_DIR) - $(MAKE) all -endif - -clean: - rm -rf build libpayload nvramcui.elf - -distclean: clean - rm -rf .config .config.old - -.PHONY: all clean distclean +ARCH = x86_32 +OBJS = $(obj)/nvramcui.o +TARGET = $(obj)/nvramcui.elf +include ../libpayload/Makefile.payload -- To view, visit https://review.coreboot.org/c/coreboot/+/47636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34bf659c1a069ccc27ca613bbf86780d4da49259 Gerrit-Change-Number: 47636 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 13

Change in coreboot[master]: coreinfo: Use libpayload's new `Makefile.payload`
by Nico Huber (Code Review) 07 Feb '21

07 Feb '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47634 ) Change subject: coreinfo: Use libpayload's new `Makefile.payload` ...................................................................... coreinfo: Use libpayload's new `Makefile.payload` Change-Id: I388d60e6f3aeb2184966152f0934845d42834de0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/coreinfo/.gitignore M payloads/coreinfo/Makefile 2 files changed, 34 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47634/1 diff --git a/payloads/coreinfo/.gitignore b/payloads/coreinfo/.gitignore index 101045e..868da49 100644 --- a/payloads/coreinfo/.gitignore +++ b/payloads/coreinfo/.gitignore @@ -1,2 +1,2 @@ -lpbuild/ -lp.config* +libpayload/ +.lp.config* diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index cd58f39..0e6bf28 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -1,23 +1,38 @@ ## SPDX-License-Identifier: GPL-2.0-only src := $(CURDIR) +obj := build + srctree := $(src) srck := $(src)/../../util/kconfig -coreinfo_obj := $(src)/build objk := $(src)/build/util/kconfig -ifeq ($(filter %clean,$(MAKECMDGOALS)),) -export KERNELVERSION := 0.1.0 -export KCONFIG_AUTOHEADER := $(coreinfo_obj)/config.h -export KCONFIG_AUTOCONFIG := $(coreinfo_obj)/auto.conf -export KCONFIG_DEPENDENCIES := $(coreinfo_obj)/auto.conf.cmd -export KCONFIG_SPLITCONFIG := $(coreinfo_obj)/config -export KCONFIG_TRISTATE := $(coreinfo_obj)/tristate.conf -export KCONFIG_CONFIG := $(CURDIR)/.config -export KCONFIG_NEGATIVES := 1 -export Kconfig := Kconfig +LIBPAYLOAD_DEFCONFIG ?= $(src)/../libpayload/configs/defconfig-tinycurses -export V := $(V) +PAYLOAD_DEPS := $(obj)/config.h + +OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \ + nvram_module.o bootlog_module.o ramdump_module.o \ + multiboot_module.o cbfs_module.o timestamps_module.o coreinfo.o +OBJS = $(patsubst %,$(obj)/%,$(OBJECTS)) +TARGET = $(obj)/coreinfo.elf + +ARCH := x86_32 + +all: real-all + +include ../libpayload/Makefile.payload + +ifeq ($(filter %clean,$(MAKECMDGOALS)),) +export KERNELVERSION := 0.1.0 +export KCONFIG_AUTOHEADER := $(obj)/config.h +export KCONFIG_AUTOCONFIG := $(obj)/auto.conf +export KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd +export KCONFIG_SPLITCONFIG := $(obj)/config +export KCONFIG_TRISTATE := $(obj)/tristate.conf +export KCONFIG_CONFIG := $(CURDIR)/.config +export KCONFIG_NEGATIVES := 1 +export Kconfig := Kconfig CONFIG_SHELL := sh KBUILD_DEFCONFIG := configs/defconfig @@ -25,52 +40,12 @@ HAVE_DOTCONFIG := $(wildcard .config) MAKEFLAGS += -rR --no-print-directory -# Make is silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -.SILENT: -endif - HOSTCC ?= gcc HOSTCXX ?= g++ HOSTCFLAGS := -I$(srck) -I$(objk) HOSTCXXFLAGS := -I$(srck) -I$(objk) -LIBPAYLOAD_PATH := $(realpath ../libpayload) -LIBPAYLOAD_OBJ := $(coreinfo_obj)/libpayload -HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_OBJ)/lib/libpayload.a) -LIBPAYLOAD_CONFIG ?= configs/defconfig-tinycurses -OBJCOPY ?= objcopy - -INCLUDES = -I$(coreinfo_obj) -include $(LIBPAYLOAD_OBJ)/include/kconfig.h -I$(src)/../../src/commonlib/include -OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \ - nvram_module.o bootlog_module.o ramdump_module.o \ - multiboot_module.o cbfs_module.o timestamps_module.o coreinfo.o -OBJS = $(patsubst %,$(coreinfo_obj)/%,$(OBJECTS)) -TARGET = $(coreinfo_obj)/coreinfo.elf - -all: real-all - -# in addition to the dependency below, create the file if it doesn't exist -# to silence warnings about a file that would be generated anyway. -$(if $(wildcard .xcompile),,$(eval $(shell ../../util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) -.xcompile: ../../util/xcompile/xcompile - $< $(XGCCPATH) > $@.tmp - \mv -f $@.tmp $@ 2> /dev/null || rm -f $@.tmp $@ - -CONFIG_COMPILER_GCC := y -ARCH-y := x86_32 - -include .xcompile - -CC := $(CC_$(ARCH-y)) -AS := $(AS_$(ARCH-y)) -OBJCOPY := $(OBJCOPY_$(ARCH-y)) - -LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc -LPAS := AS="$(AS)" $(LIBPAYLOAD_OBJ)/bin/lpas - -CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror -CFLAGS += -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) +CFLAGS += -I$(obj) -I../../src/commonlib/include ifneq ($(strip $(HAVE_DOTCONFIG)),) include $(src)/.config @@ -80,21 +55,6 @@ CFLAGS += -flto endif -$(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload - printf " LPCC $(subst $(CURDIR)/,,$(@)) (LINK)\n" - $(LPCC) $(CFLAGS) -o $@ $(OBJS) - $(OBJCOPY) --only-keep-debug $@ $(TARGET).debug - $(OBJCOPY) --strip-debug $@ - $(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ - -$(coreinfo_obj)/%.S.o: $(src)/%.S libpayload - printf " LPAS $(subst $(CURDIR)/,,$(@))\n" - $(LPAS) -o $@ $< - -$(coreinfo_obj)/%.o: $(src)/%.c libpayload - printf " LPCC $(subst $(CURDIR)/,,$(@))\n" - $(LPCC) $(CFLAGS) -c -o $@ $< - else real-all: config endif @@ -103,22 +63,10 @@ $(MAKE) olddefconfig $(MAKE) all -ifneq ($(strip $(HAVE_LIBPAYLOAD)),) -libpayload: - printf "Found Libpayload $(LIBPAYLOAD_OBJ).\n" -else -LPOPTS=obj="$(CURDIR)/lpbuild" DOTCONFIG="$(CURDIR)/lp.config" -libpayload: - printf "Building libpayload @ $(LIBPAYLOAD_PATH).\n" - $(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) distclean coreinfo_obj=$(coreinfo_obj)/libptmp - $(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) defconfig KBUILD_DEFCONFIG=$(LIBPAYLOAD_CONFIG) - $(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) install DESTDIR=$(coreinfo_obj) -endif - -$(coreinfo_obj)/config.h: +$(obj)/config.h: $(MAKE) oldconfig -$(shell mkdir -p $(coreinfo_obj) $(objk)/lxdialog $(KCONFIG_SPLITCONFIG)) +$(shell mkdir -p $(objk)/lxdialog $(KCONFIG_SPLITCONFIG)) include $(srck)/Makefile @@ -126,11 +74,8 @@ else -clean: - rm -rf build lpbuild .xcompile - distclean: clean - rm -f .config* lp.config* + rm -f .config* -.PHONY: clean distclean +.PHONY: distclean endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I388d60e6f3aeb2184966152f0934845d42834de0 Gerrit-Change-Number: 47634 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: libpayload: Add a Makefile for in-tree payloads
by Nico Huber (Code Review) 07 Feb '21

07 Feb '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47633 ) Change subject: libpayload: Add a Makefile for in-tree payloads ...................................................................... libpayload: Add a Makefile for in-tree payloads The new `Makefile.payload` can be included by the Makefiles of pay- loads for in-tree builds. The basic idea is to use libpayload's build results without the `make install` step, and to ensure incre- mental builds work. For instance, if libpayload's code changes, a `make` in for the payload would automatically update the libpayload build and rebuild the payload. But if there are no code changes in libpayload, only updated files of the payload will be re-build. The configuration of libpayload is supposed to be automatically generated from a `defconfig` file. If this `defconfig` changes, libpayload and the payload will be re-build. Change-Id: If5319f1bf0bcd09964416237c5cf7f8e59f487a2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- A payloads/libpayload/Makefile.payload 1 file changed, 123 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/47633/1 diff --git a/payloads/libpayload/Makefile.payload b/payloads/libpayload/Makefile.payload new file mode 100644 index 0000000..1d7a39b --- /dev/null +++ b/payloads/libpayload/Makefile.payload @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: BSD-3-Clause + +# +# This file is meant to be included by in-tree payloads +# to provide default targets for incremental builds. +# +# Variables with file names and directory overrides have +# to be defined in advance for proper dependency tracking. +# Then, include this file. e.g +# +# obj := output +# OBJS := $(obj)/payload.o +# TARGET := $(obj)/payload.elf +# include ../path/to/libpayload/Makefile.payload +# + +# Find relative path to libpayload (where this Makefile resides). +LIBPAYLOAD_SRC := $(dir $(lastword $(MAKEFILE_LIST))) + +# Build dir and config for libpayload. Need absolute +# paths to pass to libpayload's sub-make. +LIBPAYLOAD_OBJ ?= $(CURDIR)/libpayload +LIBPAYLOAD_DOTCONFIG ?= $(CURDIR)/.lp.config +LIBPAYLOAD_DEFCONFIG ?= $(CURDIR)/$(LIBPAYLOAD_SRC)/configs/defconfig + +# Some default dependencies for all targets: +DEFAULT_DEPS := $(LIBPAYLOAD_OBJ)/libpayload.a +DEFAULT_DEPS += Makefile $(lastword $(MAKEFILE_LIST)) +DEFAULT_DEPS += $(PAYLOAD_DEPS) + +obj ?= build + +ARCH ?= +OBJS ?= +CCACHE ?= + +CFLAGS = $(GCC_CFLAGS_$(ARCH)) +CFLAGS += -Os -ffreestanding +CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror + +# Make is silent per default, but `make V=1` will show all calls. +Q:=@ +ifneq ($(V),1) +ifneq ($(Q),) +.SILENT: +MAKEFLAGS += -s +endif +endif +export V + +ifeq ($(filter %clean,$(MAKECMDGOALS)),) + +# In addition to the dependency below, create the file if it doesn't exist +# to silence warnings about a file that would be generated anyway. +$(if $(wildcard .xcompile),,$(eval $(shell \ + $(LIBPAYLOAD_SRC)../../util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) +.xcompile: $(LIBPAYLOAD_SRC)../../util/xcompile/xcompile + $< $(XGCCPATH) > $@.tmp + \mv -f $@.tmp $@ 2> /dev/null || rm -f $@.tmp $@ +include .xcompile + +# `lpgcc` in in-tree mode: +LPGCC = CC="$(CCACHE) $(GCC_CC_$(ARCH))" +LPGCC += _OBJ="$(LIBPAYLOAD_OBJ)" +LPGCC += $(LIBPAYLOAD_SRC)/bin/lpgcc + +LPAS = AS="$(AS_$(ARCH))" +LPAS += $(LIBPAYLOAD_SRC)/bin/lpas + +OBJCOPY = $(OBJCOPY_$(ARCH)) + +$(TARGET): + +$(obj)/%.elf: $(OBJS) $(DEFAULT_DEPS) + @printf " LPGCC $(subst $(obj)/,,$@)\n" + $(LPGCC) $(CFLAGS) -o $@ $(OBJS) + $(OBJCOPY) --only-keep-debug $@ $@.debug + $(OBJCOPY) --strip-debug $@ + $(OBJCOPY) --add-gnu-debuglink=$@.debug $@ + +$(obj)/%.o: %.c $(DEFAULT_DEPS) + @printf " LPGCC $(subst $(obj)/,,$@)\n" + $(LPGCC) $(CFLAGS) -c $< -o $@ + +$(obj)/%.S.o: %.S $(DEFAULT_DEPS) + @printf " LPAS $(subst $(obj)/,,$@)\n" + $(LPAS) $< -o $@ + +LIBPAYLOAD_OPTS := obj="$(LIBPAYLOAD_OBJ)" +LIBPAYLOAD_OPTS += DOTCONFIG="$(LIBPAYLOAD_DOTCONFIG)" +LIBPAYLOAD_OPTS += $(if $(CCACHE),CONFIG_LP_CCACHE=y) + +defconfig: lp-defconfig +lp-defconfig: $(LIBPAYLOAD_DOTCONFIG) +$(LIBPAYLOAD_DOTCONFIG): $(LIBPAYLOAD_DEFCONFIG) | $(PAYLOAD_DEPS) + $(MAKE) -C $(LIBPAYLOAD_SRC) $(LIBPAYLOAD_OPTS) \ + KBUILD_DEFCONFIG=$(LIBPAYLOAD_DEFCONFIG) defconfig + +oldconfig: lp-oldconfig +lp-oldconfig: + [ ! -f $(LIBPAYLOAD_DOTCONFIG) ] || \ + $(MAKE) -C $(LIBPAYLOAD_SRC) $(LIBPAYLOAD_OPTS) oldconfig + +$(LIBPAYLOAD_OBJ)/libpayload.a: lp-defconfig + $(MAKE) -C $(LIBPAYLOAD_SRC) $(LIBPAYLOAD_OPTS) + +$(shell mkdir -p $(sort $(dir $(OBJS)))) + +.PHONY: oldconfig lp-oldconfig defconfig lp-defconfig + +else # %clean,$(MAKECMDGOALS) + +default-payload-clean: + rm -rf $(obj) $(LIBPAYLOAD_OBJ) .xcompile +clean: default-payload-clean + +default-payload-distclean: clean + rm -f $(LIBPAYLOAD_DOTCONFIG) $(LIBPAYLOAD_DOTCONFIG).old +distclean: default-payload-distclean + +.PHONY: default-payload-clean clean default-payload-distclean distclean + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5319f1bf0bcd09964416237c5cf7f8e59f487a2 Gerrit-Change-Number: 47633 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: nvramcui: Unexport COREBOOT_EXPORTS
by Nico Huber (Code Review) 07 Feb '21

07 Feb '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48940 ) Change subject: nvramcui: Unexport COREBOOT_EXPORTS ...................................................................... nvramcui: Unexport COREBOOT_EXPORTS coreboot's Makefile exports a lot of variables that influence make sub- processes (e.g. for Kconfig). We don't want these variables leak into sub-processes for (lib)payload builds, hence unexport them. Change-Id: I8da2d8db6238d456723b9c22bee80c62e97027b0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/nvramcui/Makefile 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48940/1 diff --git a/payloads/nvramcui/Makefile b/payloads/nvramcui/Makefile index 269d558..ebc48de 100644 --- a/payloads/nvramcui/Makefile +++ b/payloads/nvramcui/Makefile @@ -1,3 +1,5 @@ +unexport $(COREBOOT_EXPORTS) + LIBPAYLOAD_DIR=$(CURDIR)/libpayload XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile # build libpayload and put .config file in $(CURDIR) instead of ../libpayload -- To view, visit https://review.coreboot.org/c/coreboot/+/48940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8da2d8db6238d456723b9c22bee80c62e97027b0 Gerrit-Change-Number: 48940 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: coreinfo: Unexport COREBOOT_EXPORTS
by Nico Huber (Code Review) 07 Feb '21

07 Feb '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48939 ) Change subject: coreinfo: Unexport COREBOOT_EXPORTS ...................................................................... coreinfo: Unexport COREBOOT_EXPORTS coreboot's Makefile exports a lot of variables that influence make sub- processes (e.g. for Kconfig). We don't want these variables leak into sub-processes for (lib)payload builds, hence unexport them. Change-Id: I7d65c0aa6d4550bd6600c437e838339af69496da Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/coreinfo/Makefile 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/48939/1 diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index cd58f39..8d2f3c6 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only +unexport $(COREBOOT_EXPORTS) + src := $(CURDIR) srctree := $(src) srck := $(src)/../../util/kconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/48939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d65c0aa6d4550bd6600c437e838339af69496da Gerrit-Change-Number: 48939 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: Fixed hostname in `lshw` output examples
by Alexey Vazhnov (Code Review) 07 Feb '21

07 Feb '21

Alexey Vazhnov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50369 ) Change subject: Fixed hostname in `lshw` output examples ...................................................................... Fixed hostname in `lshw` output examples Change-Id: Ia9a7dbd4d20bb32a52a906365bf0f8238fd954f8 Signed-off-by: Alexey Vazhnov <vazhnov(a)boot-keys.org> --- M Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt M Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/50369/1 diff --git a/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt b/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt index 98a152f..108af64 100644 --- a/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt +++ b/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt @@ -1,4 +1,4 @@ -lenovo-z370 +my-desktop description: Desktop Computer product: GA-G41M-ES2L vendor: GIGABYTE diff --git a/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt b/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt index 1f28646..45776b2 100644 --- a/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt +++ b/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt @@ -1,4 +1,4 @@ -lenovo-z370 +my-desktop description: Desktop Computer product: G41M-ES2L vendor: Gigabyte Technology Co., Ltd. -- To view, visit https://review.coreboot.org/c/coreboot/+/50369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9a7dbd4d20bb32a52a906365bf0f8238fd954f8 Gerrit-Change-Number: 50369 Gerrit-PatchSet: 1 Gerrit-Owner: Alexey Vazhnov <vazhnov(a)boot-keys.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cyan/var/terra: Convert to ASL 2.0
by Angel Pons (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50320 ) Change subject: mb/google/cyan/var/terra: Convert to ASL 2.0 ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50320/comment/51485b7c_eecbb4d5 PS1, Line 7: mb/cyan/variants/terra/include/variant/acpi > mb/google/cyan/var/terra Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6158943c61b3e2156a2ebbf96aa73e7cf87a7e Gerrit-Change-Number: 50320 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 07 Feb 2021 15:41:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Initial documentation for Gigabyte GA-G41M-ES2L
by Alexey Vazhnov (Code Review) 07 Feb '21

07 Feb '21

Alexey Vazhnov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50368 ) Change subject: Initial documentation for Gigabyte GA-G41M-ES2L ...................................................................... Initial documentation for Gigabyte GA-G41M-ES2L Not finished yet, just to check is format ok for coreboot. Change-Id: Ib45cfea15b43d7399e9d209f7ba7c6b24fe860dd Signed-off-by: Alexey Vazhnov <vazhnov(a)boot-keys.org> --- A Documentation/mainboard/gigabyte/ga-g41m-es2l.md A Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt A Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt M Documentation/mainboard/index.md A configs/config.gigabyte_ga-g41m-es2l 5 files changed, 957 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/50368/1 diff --git a/Documentation/mainboard/gigabyte/ga-g41m-es2l.md b/Documentation/mainboard/gigabyte/ga-g41m-es2l.md new file mode 100644 index 0000000..eeca580 --- /dev/null +++ b/Documentation/mainboard/gigabyte/ga-g41m-es2l.md @@ -0,0 +1,205 @@ +# Gigabyte GA-G41M-ES2L rev 1.1 + +This page describes how to use coreboot on the [Gigabyte GA-G41M-ES2L rev 1.1](http://www.gigabyte.com/Motherboard/GA-G41M-ES2L-rev-11#ov) mainboard. + +This motherboard [also works](https://libreboot.org/docs/install/ga-g41m-es2l.html) with Libreboot. + +Components: + +- Intel ICH7 +- DUAL BIOS +- BIOS flash chips: SST25VF080B (8 Mbit SPI) +- Realtek RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 02), driver i915 +- Audio device: Realtek ALC887 / GA-D525TUD, driver snd\_hda\_intel + +## Preparation + +```eval_rst +For more datails how to get sources and build the toolchain, see :doc:`../../tutorial/part1`. +``` + +### Devuan 4 Chimaera + +This probably works also for any fresh Debian/Ubuntu-based distros. + +Install tools and libraries needed for coreboot: + +```shell +sudo apt-get -V install bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev wget python2 python-is-python2 flashrom +``` + +### Get sources + +You need about 700 MB disk space for sources only and ~2GB disk space for sources + build results + +```shell +git clone --recursive https://review.coreboot.org/coreboot.git +``` + +### Build toolchain + +Build coreboot cross-compilers for all platforms (or use `ANY_TOOLCHAIN=y`, but this not recommended): + +```shell +make crossgcc CPUS=2 +``` + +### Save MAC-address of internal LAN + +Run `ip -c link show`, you will find MAC-address like 6c:f0:49:XX:XX:XX + +``` +1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000 + link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00 +2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast state UP mode DEFAULT group default qlen 1000 + link/ether 6c:f0:49:XX:XX:XX brd ff:ff:ff:ff:ff:ff +``` + +## Configure + +This will create `payloads/external/SeaBIOS/seabios/`: + +```shell +cd payloads/external/SeaBIOS/ +make config +``` + +Create file in the root of repository, like `.config_seabios`: + +```shell +CONFIG_COREBOOT=y +CONFIG_ATA_DMA=y +CONFIG_VGA_COREBOOT=y +``` + +Edit file `configs/config.gigabyte_ga-g41m-es2l`, replace `CONFIG_REALTEK_8168_MACADDRESS`. + +Run + +```shell +make defconfig KBUILD_DEFCONFIG="configs/config.gigabyte_ga-g41m-es2l" +``` + +## Build + +```shell +make +``` + +Example of last part in the output: + +``` + CBFSPRINT coreboot.rom + +FMAP REGION: COREBOOT +Name Offset Type Size Comp +cbfs master header 0x0 cbfs header 32 none +fallback/romstage 0x80 stage 62316 none +cpu_microcode_blob.bin 0xf480 microcode 180224 none +fallback/ramstage 0x3b500 stage 98745 none +vgaroms/seavgabios.bin 0x53700 raw 28672 none +config 0x5a740 raw 301 none +revision 0x5a8c0 raw 675 none +build_info 0x5abc0 raw 103 none +fallback/dsdt.aml 0x5ac80 raw 8447 none +rt8168-macaddress 0x5cdc0 raw 17 none +vbt.bin 0x5ce40 raw 802 LZMA (1899 decompressed) +cmos.default 0x5d1c0 cmos_default 256 none +cmos_layout.bin 0x5d300 cmos_layout 1040 none +fallback/postcar 0x5d740 stage 20844 none +fallback/payload 0x62900 simple elf 70270 none +payload_config 0x73bc0 raw 1699 none +payload_revision 0x742c0 raw 237 none +(empty) 0x74400 null 482904 none +bootblock 0xea280 bootblock 23360 none + HOSTCC cbfstool/ifwitool.o + HOSTCC cbfstool/ifwitool (link) + +Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L) +``` + +## Flashing coreboot + +```eval_rst +In addition to the information here, please see the +:doc:`../../flash_tutorial/index`. +``` + +### Do backup + +```shell +sudo flashrom -p internal:dualbiosindex=0 -r m_bios.rom +sudo flashrom -p internal:dualbiosindex=0 -v m_bios.rom +sudo flashrom -p internal:dualbiosindex=1 -r b_bios.rom +sudo flashrom -p internal:dualbiosindex=1 -v b_bios.rom +``` + +If access error appeared, then add `iomem=relaxed` to linux kernel parameters and restart your Linux system. + +You can also repeat backup and compare checksums manually. + +### Write new flash image + +```shell +sudo flashrom -p internal:dualbiosindex=0 -w build/coreboot.rom +sudo flashrom -p internal:dualbiosindex=1 -E +sudo flashrom -p internal:dualbiosindex=0 -v build/coreboot.rom +``` + +## Status + +### Build from latest sources 2021-01-28 2fae1c049407c11e393430de762d5ffa28b1a82e + +#### Known issues + +#### Working + +- RAM 2x1GB DDR2 PC2-6400 Kingston KTC1G-UDIMM +- CPU E8400 +- ACPI +- CPU frequency scaling +- flashrom under coreboot +- Gigabit Ethernet +- Hardware monitoring +- Integrated graphics +- SATA + +Sensors: + +``` +coretemp-isa-0000 +Adapter: ISA adapter +Core 0: +27.0°C (high = +80.0°C, crit = +100.0°C) +Core 1: +33.0°C (high = +80.0°C, crit = +100.0°C) +``` + +#### Not tested + +- KVM virtualization +- Onboard audio +- PCI +- PCIe +- PS/2 keyboard mouse (during payload, bootloader) +- Serial port +- SuperIO based fan control +- USB (disabling XHCI controller makes to work as fallback USB2.0 ports) +- IOMMU + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| SuperIO | ITE IT8728F | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------------------------+ +``` + diff --git a/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt b/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt new file mode 100644 index 0000000..98a152f --- /dev/null +++ b/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt @@ -0,0 +1,372 @@ +lenovo-z370 + description: Desktop Computer + product: GA-G41M-ES2L + vendor: GIGABYTE + version: 1.0 + serial: 123456789 + width: 64 bits + capabilities: smbios-3.0.0 dmi-3.0.0 smp vsyscall32 + configuration: boot=normal chassis=desktop + *-core + description: Motherboard + product: GA-G41M-ES2L + vendor: GIGABYTE + physical id: 0 + version: 1.0 + serial: 123456789 + *-firmware + description: BIOS + vendor: coreboot + physical id: 0 + version: 4.13-1531-g2fae1c0494 + date: 01/29/2021 + size: 1MiB + capacity: 1MiB + capabilities: pci pcmcia upgrade bootselect acpi + *-cpu + description: CPU + product: Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz + vendor: Intel Corp. + physical id: 4 + bus info: cpu@0 + version: Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz + slot: CPU0 + size: 2943MHz + capacity: 3GHz + width: 64 bits + capabilities: fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ht tm pbe syscall nx x86-64 constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm pti tpr_shadow vnmi flexpriority vpid dtherm cpufreq + *-cache + description: L2 cache + physical id: 7 + slot: CACHE2 + size: 6MiB + capacity: 6MiB + capabilities: internal unified + configuration: level=2 + *-memory + description: System memory + physical id: 1 + size: 2GiB + *-pci + description: Host bridge + product: 4 Series Chipset DRAM Controller + vendor: Intel Corporation + physical id: 100 + bus info: pci@0000:00:00.0 + version: 03 + width: 32 bits + clock: 33MHz + *-pci:0 + description: PCI bridge + product: 4 Series Chipset PCI Express Root Port + vendor: Intel Corporation + physical id: 1 + bus info: pci@0000:00:01.0 + version: 03 + width: 32 bits + clock: 33MHz + capabilities: pci pm msi pciexpress normal_decode bus_master cap_list + configuration: driver=pcieport + resources: irq:24 + *-display:0 + description: VGA compatible controller + product: 4 Series Chipset Integrated Graphics Controller + vendor: Intel Corporation + physical id: 2 + bus info: pci@0000:00:02.0 + version: 03 + width: 64 bits + clock: 33MHz + capabilities: msi pm vga_controller bus_master cap_list rom + configuration: driver=i915 latency=0 + resources: irq:16 memory:90000000-903fffff memory:80000000-8fffffff ioport:20a0(size=8) memory:c0000-dffff + *-display:1 UNCLAIMED + description: Display controller + product: 4 Series Chipset Integrated Graphics Controller + vendor: Intel Corporation + physical id: 2.1 + bus info: pci@0000:00:02.1 + version: 03 + width: 64 bits + clock: 33MHz + capabilities: pm cap_list + configuration: latency=0 + resources: memory:90400000-904fffff + *-multimedia + description: Audio device + product: NM10/ICH7 Family High Definition Audio Controller + vendor: Intel Corporation + physical id: 1b + bus info: pci@0000:00:1b.0 + version: 01 + width: 64 bits + clock: 33MHz + capabilities: pm msi pciexpress bus_master cap_list + configuration: driver=snd_hda_intel latency=0 + resources: irq:28 memory:90700000-90703fff + *-pci:1 + description: PCI bridge + product: NM10/ICH7 Family PCI Express Port 1 + vendor: Intel Corporation + physical id: 1c + bus info: pci@0000:00:1c.0 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: pci pciexpress msi pm normal_decode bus_master cap_list + configuration: driver=pcieport + resources: irq:25 + *-pci:2 + description: PCI bridge + product: NM10/ICH7 Family PCI Express Port 2 + vendor: Intel Corporation + physical id: 1c.1 + bus info: pci@0000:00:1c.1 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: pci pciexpress msi pm normal_decode bus_master cap_list + configuration: driver=pcieport + resources: irq:26 ioport:1000(size=4096) memory:90600000-906fffff ioport:90500000(size=1048576) + *-network + description: Ethernet interface + product: RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller + vendor: Realtek Semiconductor Co., Ltd. + physical id: 0 + bus info: pci@0000:03:00.0 + logical name: eth0 + version: 02 + serial: 6c:f0:49:a3:e3:d5 + size: 1Gbit/s + capacity: 1Gbit/s + width: 64 bits + clock: 33MHz + capabilities: pm msi pciexpress msix vpd bus_master cap_list rom ethernet physical tp mii 10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd autonegotiation + configuration: autonegotiation=on broadcast=yes driver=r8169 driverversion=5.10.0-2-amd64 duplex=full ip=192.168.155.136 latency=0 link=yes multicast=yes port=MII speed=1Gbit/s + resources: irq:17 ioport:1000(size=256) memory:90510000-90510fff memory:90500000-9050ffff memory:90600000-9060ffff + *-usb:0 + description: USB controller + product: NM10/ICH7 Family USB UHCI Controller #1 + vendor: Intel Corporation + physical id: 1d + bus info: pci@0000:00:1d.0 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: uhci bus_master + configuration: driver=uhci_hcd latency=0 + resources: irq:23 ioport:2000(size=32) + *-usb:1 + description: USB controller + product: NM10/ICH7 Family USB UHCI Controller #2 + vendor: Intel Corporation + physical id: 1d.1 + bus info: pci@0000:00:1d.1 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: uhci bus_master + configuration: driver=uhci_hcd latency=0 + resources: irq:19 ioport:2020(size=32) + *-usb:2 + description: USB controller + product: NM10/ICH7 Family USB UHCI Controller #3 + vendor: Intel Corporation + physical id: 1d.2 + bus info: pci@0000:00:1d.2 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: uhci bus_master + configuration: driver=uhci_hcd latency=0 + resources: irq:18 ioport:2040(size=32) + *-usb:3 + description: USB controller + product: NM10/ICH7 Family USB UHCI Controller #4 + vendor: Intel Corporation + physical id: 1d.3 + bus info: pci@0000:00:1d.3 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: uhci bus_master + configuration: driver=uhci_hcd latency=0 + resources: irq:16 ioport:2060(size=32) + *-usb:4 + description: USB controller + product: NM10/ICH7 Family USB2 EHCI Controller + vendor: Intel Corporation + physical id: 1d.7 + bus info: pci@0000:00:1d.7 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: pm debug ehci bus_master cap_list + configuration: driver=ehci-pci latency=0 + resources: irq:23 memory:90704000-907043ff + *-pci:3 + description: PCI bridge + product: 82801 PCI Bridge + vendor: Intel Corporation + physical id: 1e + bus info: pci@0000:00:1e.0 + version: e1 + width: 32 bits + clock: 33MHz + capabilities: pci subtractive_decode bus_master cap_list + *-isa + description: ISA bridge + product: 82801GB/GR (ICH7 Family) LPC Interface Bridge + vendor: Intel Corporation + physical id: 1f + bus info: pci@0000:00:1f.0 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: isa bus_master cap_list + configuration: driver=lpc_ich latency=0 + resources: irq:0 + *-ide:0 + description: IDE interface + product: 82801G (ICH7 Family) IDE Controller + vendor: Intel Corporation + physical id: 1f.1 + bus info: pci@0000:00:1f.1 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: ide isa_compat_mode pci_native_mode bus_master + configuration: driver=ata_piix latency=0 + resources: irq:18 ioport:1f0(size=8) ioport:3f6 ioport:170(size=8) ioport:376 ioport:2080(size=16) + *-ide:1 + description: IDE interface + product: NM10/ICH7 Family SATA Controller [IDE mode] + vendor: Intel Corporation + physical id: 1f.2 + bus info: pci@0000:00:1f.2 + logical name: scsi2 + version: 01 + width: 32 bits + clock: 66MHz + capabilities: ide pm isa_compat_mode pci_native_mode bus_master cap_list emulated + configuration: driver=ata_piix latency=0 + resources: irq:19 ioport:20b8(size=8) ioport:20d0(size=4) ioport:20c0(size=8) ioport:20d4(size=4) ioport:2090(size=16) + *-disk + description: ATA Disk + product: WDC WD5000BPVT-2 + vendor: Western Digital + physical id: 0.0.0 + bus info: scsi@2:0.0.0 + logical name: /dev/sda + version: 1A03 + serial: WD-WXD1E71MYND4 + size: 465GiB (500GB) + capabilities: gpt-1.00 partitioned partitioned:gpt + configuration: ansiversion=5 guid=868a1c85-f309-4f3d-8282-6b5c4c373275 logicalsectorsize=512 sectorsize=4096 + *-volume:0 + description: BIOS Boot partition + vendor: EFI + physical id: 1 + bus info: scsi@2:0.0.0,1 + logical name: /dev/sda1 + serial: bdedbd57-d535-4e89-807b-da17f2b1feee + capacity: 10239KiB + capabilities: nofs + *-volume:1 + description: EFI partition + vendor: Linux + physical id: 2 + bus info: scsi@2:0.0.0,2 + logical name: /dev/sda2 + version: 1.0 + serial: 0d465ffa-a807-47fc-b9f5-3faa6cefd564 + size: 1GiB + capabilities: extended_attributes large_files ext2 initialized + configuration: filesystem=ext2 label=Ubuntu_boot lastmountpoint=/boot modified=2020-06-27 10:20:50 mounted=2020-06-27 10:01:33 name=Ubuntu_boot state=clean + *-volume:2 + description: EFI partition + vendor: Linux + physical id: 3 + bus info: scsi@2:0.0.0,3 + logical name: /dev/sda3 + version: 1.0 + serial: 08c9dedc-878d-4650-a3f8-0e41a6fb1fdb + size: 1GiB + capabilities: extended_attributes large_files ext2 initialized + configuration: filesystem=ext2 label=Gentoo_boot modified=2020-06-27 10:00:47 mounted=2020-06-27 09:26:45 name=Gentoo_boot state=clean + *-volume:3 + description: EFI partition + physical id: 4 + bus info: scsi@2:0.0.0,4 + logical name: /dev/sda4 + serial: 37942d50-6c0b-4aeb-a2f9-056d9963a936 + size: 102GiB + capacity: 102GiB + width: 2532569072 bits + capabilities: encrypted luks initialized + configuration: bits=15417470960 filesystem=luks hash=sha256 version=2 + *-volume:4 + description: EXT4 volume + vendor: Linux + physical id: 5 + bus info: scsi@2:0.0.0,5 + logical name: /dev/sda5 + logical name: / + version: 1.0 + serial: 23cbec55-6ee6-4ec4-9d41-a9f79ee39da7 + size: 93GiB + capabilities: journaled extended_attributes large_files huge_files dir_nlink recover 64bit extents ext4 ext2 initialized + configuration: created=2020-06-13 13:44:46 filesystem=ext4 label=Devuan_root lastmountpoint=/ modified=2021-01-30 16:43:04 mount.fstype=ext4 mount.options=rw,noatime,nodiratime,errors=remount-ro mounted=2021-01-30 16:43:17 name=Devuan_root state=mounted + *-volume:5 + description: Linux swap volume + vendor: Linux + physical id: 6 + bus info: scsi@2:0.0.0,6 + logical name: /dev/sda6 + version: 1 + serial: bca5b558-f37c-40f3-abbb-b5395036a215 + size: 2047MiB + capacity: 2047MiB + capabilities: nofs swap initialized + configuration: filesystem=swap label=Swap2G pagesize=4095 + *-serial + description: SMBus + product: NM10/ICH7 Family SMBus Controller + vendor: Intel Corporation + physical id: 1f.3 + bus info: pci@0000:00:1f.3 + version: 01 + width: 32 bits + clock: 33MHz + configuration: driver=i801_smbus latency=0 + resources: irq:19 ioport:400(size=32) + *-pnp00:00 + product: PnP device PNP0c02 + physical id: 2 + capabilities: pnp + configuration: driver=system + *-pnp00:01 + product: PnP device PNP0103 + physical id: 3 + capabilities: pnp + configuration: driver=system + *-pnp00:02 + product: PnP device PNP0c02 + physical id: 5 + capabilities: pnp + configuration: driver=system + *-pnp00:03 + product: PnP device PNP0b00 + physical id: 6 + capabilities: pnp + configuration: driver=rtc_cmos + *-pnp00:04 + product: PnP device PNP0303 + physical id: 7 + capabilities: pnp + configuration: driver=i8042 kbd + *-pnp00:05 + product: PnP device PNP0f13 + physical id: 8 + capabilities: pnp + configuration: driver=i8042 aux diff --git a/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt b/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt new file mode 100644 index 0000000..1f28646 --- /dev/null +++ b/Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt @@ -0,0 +1,370 @@ +lenovo-z370 + description: Desktop Computer + product: G41M-ES2L + vendor: Gigabyte Technology Co., Ltd. + width: 64 bits + capabilities: smbios-2.4 dmi-2.4 smp vsyscall32 + configuration: boot=normal chassis=desktop uuid=00000000-0000-0000-0000-6CF049A3E3D5 + *-core + description: Motherboard + product: G41M-ES2L + vendor: Gigabyte Technology Co., Ltd. + physical id: 0 + *-firmware + description: BIOS + vendor: Award Software International, Inc. + physical id: 0 + version: F9 + date: 06/21/2010 + size: 128KiB + capacity: 1MiB + capabilities: pci pnp apm upgrade shadowing cdboot bootselect edd int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int5printscreen int9keyboard int14serial int17printer int10video acpi usb ls120boot zipboot biosbootspecification + *-cpu + description: CPU + product: Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz + vendor: Intel Corp. + physical id: 4 + bus info: cpu@0 + version: Intel(R) Core(TM)2 Duo CPU + slot: Socket 775 + size: 2631MHz + capacity: 4GHz + width: 64 bits + clock: 333MHz + capabilities: fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ht tm pbe syscall nx x86-64 constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm pti tpr_shadow vnmi flexpriority vpid dtherm cpufreq + *-cache:0 + description: L1 cache + physical id: a + slot: Internal Cache + size: 64KiB + capacity: 64KiB + capabilities: synchronous internal write-back + configuration: level=1 + *-cache:1 + description: L2 cache + physical id: b + slot: External Cache + size: 6MiB + capabilities: synchronous internal write-back + configuration: level=2 + *-memory + description: System Memory + physical id: 19 + slot: System board or motherboard + size: 2GiB + *-bank:0 + description: DIMM 800 MHz (1.2 ns) + physical id: 0 + slot: A0 + size: 1GiB + width: 64 bits + clock: 800MHz (1.2ns) + *-bank:1 + description: DIMM [empty] + physical id: 1 + slot: A1 + *-bank:2 + description: DIMM 800 MHz (1.2 ns) + physical id: 2 + slot: A2 + size: 1GiB + width: 64 bits + clock: 800MHz (1.2ns) + *-bank:3 + description: DIMM [empty] + physical id: 3 + slot: A3 + *-pci + description: Host bridge + product: 4 Series Chipset DRAM Controller + vendor: Intel Corporation + physical id: 100 + bus info: pci@0000:00:00.0 + version: 03 + width: 32 bits + clock: 33MHz + *-display + description: VGA compatible controller + product: 4 Series Chipset Integrated Graphics Controller + vendor: Intel Corporation + physical id: 2 + bus info: pci@0000:00:02.0 + version: 03 + width: 64 bits + clock: 33MHz + capabilities: msi pm vga_controller bus_master cap_list rom + configuration: driver=i915 latency=0 + resources: irq:16 memory:fd800000-fdbfffff memory:d0000000-dfffffff ioport:ff00(size=8) memory:c0000-dffff + *-multimedia + description: Audio device + product: NM10/ICH7 Family High Definition Audio Controller + vendor: Intel Corporation + physical id: 1b + bus info: pci@0000:00:1b.0 + version: 01 + width: 64 bits + clock: 33MHz + capabilities: pm msi pciexpress bus_master cap_list + configuration: driver=snd_hda_intel latency=0 + resources: irq:27 memory:fdff8000-fdffbfff + *-pci:0 + description: PCI bridge + product: NM10/ICH7 Family PCI Express Port 1 + vendor: Intel Corporation + physical id: 1c + bus info: pci@0000:00:1c.0 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: pci pciexpress msi pm normal_decode bus_master cap_list + configuration: driver=pcieport + resources: irq:24 ioport:1000(size=4096) memory:7dd00000-7defffff ioport:80000000(size=2097152) + *-pci:1 + description: PCI bridge + product: NM10/ICH7 Family PCI Express Port 2 + vendor: Intel Corporation + physical id: 1c.1 + bus info: pci@0000:00:1c.1 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: pci pciexpress msi pm normal_decode bus_master cap_list + configuration: driver=pcieport + resources: irq:25 ioport:d000(size=4096) memory:fdd00000-fddfffff ioport:fde00000(size=1048576) + *-network + description: Ethernet interface + product: RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller + vendor: Realtek Semiconductor Co., Ltd. + physical id: 0 + bus info: pci@0000:02:00.0 + logical name: eth0 + version: 02 + serial: 6c:f0:49:a3:e3:d5 + size: 1Gbit/s + capacity: 1Gbit/s + width: 64 bits + clock: 33MHz + capabilities: pm msi pciexpress msix vpd bus_master cap_list rom ethernet physical tp mii 10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd autonegotiation + configuration: autonegotiation=on broadcast=yes driver=r8169 driverversion=5.10.0-2-amd64 duplex=full ip=192.168.155.137 latency=0 link=yes multicast=yes port=MII speed=1Gbit/s + resources: irq:17 ioport:de00(size=256) memory:fdeff000-fdefffff memory:fdee0000-fdeeffff memory:fdd00000-fdd0ffff + *-usb:0 + description: USB controller + product: NM10/ICH7 Family USB UHCI Controller #1 + vendor: Intel Corporation + physical id: 1d + bus info: pci@0000:00:1d.0 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: uhci bus_master + configuration: driver=uhci_hcd latency=0 + resources: irq:23 ioport:fe00(size=32) + *-usb:1 + description: USB controller + product: NM10/ICH7 Family USB UHCI Controller #2 + vendor: Intel Corporation + physical id: 1d.1 + bus info: pci@0000:00:1d.1 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: uhci bus_master + configuration: driver=uhci_hcd latency=0 + resources: irq:19 ioport:fd00(size=32) + *-usb:2 + description: USB controller + product: NM10/ICH7 Family USB UHCI Controller #3 + vendor: Intel Corporation + physical id: 1d.2 + bus info: pci@0000:00:1d.2 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: uhci bus_master + configuration: driver=uhci_hcd latency=0 + resources: irq:18 ioport:fc00(size=32) + *-usb:3 + description: USB controller + product: NM10/ICH7 Family USB UHCI Controller #4 + vendor: Intel Corporation + physical id: 1d.3 + bus info: pci@0000:00:1d.3 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: uhci bus_master + configuration: driver=uhci_hcd latency=0 + resources: irq:16 ioport:fb00(size=32) + *-usb:4 + description: USB controller + product: NM10/ICH7 Family USB2 EHCI Controller + vendor: Intel Corporation + physical id: 1d.7 + bus info: pci@0000:00:1d.7 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: pm ehci bus_master cap_list + configuration: driver=ehci-pci latency=0 + resources: irq:23 memory:fdfff000-fdfff3ff + *-pci:2 + description: PCI bridge + product: 82801 PCI Bridge + vendor: Intel Corporation + physical id: 1e + bus info: pci@0000:00:1e.0 + version: e1 + width: 32 bits + clock: 33MHz + capabilities: pci subtractive_decode cap_list + *-isa + description: ISA bridge + product: 82801GB/GR (ICH7 Family) LPC Interface Bridge + vendor: Intel Corporation + physical id: 1f + bus info: pci@0000:00:1f.0 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: isa bus_master cap_list + configuration: driver=lpc_ich latency=0 + resources: irq:0 + *-ide:0 + description: IDE interface + product: 82801G (ICH7 Family) IDE Controller + vendor: Intel Corporation + physical id: 1f.1 + bus info: pci@0000:00:1f.1 + version: 01 + width: 32 bits + clock: 33MHz + capabilities: ide isa_compat_mode pci_native_mode bus_master + configuration: driver=ata_piix latency=0 + resources: irq:18 ioport:1f0(size=8) ioport:3f6 ioport:170(size=8) ioport:376 ioport:f800(size=16) + *-ide:1 + description: IDE interface + product: NM10/ICH7 Family SATA Controller [IDE mode] + vendor: Intel Corporation + physical id: 1f.2 + bus info: pci@0000:00:1f.2 + logical name: scsi2 + version: 01 + width: 32 bits + clock: 66MHz + capabilities: ide pm isa_compat_mode pci_native_mode bus_master cap_list emulated + configuration: driver=ata_piix latency=0 + resources: irq:19 ioport:f700(size=8) ioport:f600(size=4) ioport:f500(size=8) ioport:f400(size=4) ioport:f300(size=16) + *-disk + description: ATA Disk + product: WDC WD5000BPVT-2 + vendor: Western Digital + physical id: 0.0.0 + bus info: scsi@2:0.0.0 + logical name: /dev/sda + version: 1A03 + serial: WD-WXD1E71MYND4 + size: 465GiB (500GB) + capabilities: gpt-1.00 partitioned partitioned:gpt + configuration: ansiversion=5 guid=868a1c85-f309-4f3d-8282-6b5c4c373275 logicalsectorsize=512 sectorsize=4096 + *-volume:0 + description: BIOS Boot partition + vendor: EFI + physical id: 1 + bus info: scsi@2:0.0.0,1 + logical name: /dev/sda1 + serial: bdedbd57-d535-4e89-807b-da17f2b1feee + capacity: 10239KiB + capabilities: nofs + *-volume:1 + description: EFI partition + vendor: Linux + physical id: 2 + bus info: scsi@2:0.0.0,2 + logical name: /dev/sda2 + version: 1.0 + serial: 0d465ffa-a807-47fc-b9f5-3faa6cefd564 + size: 1GiB + capabilities: extended_attributes large_files ext2 initialized + configuration: filesystem=ext2 label=Ubuntu_boot lastmountpoint=/boot modified=2020-06-27 10:20:50 mounted=2020-06-27 10:01:33 name=Ubuntu_boot state=clean + *-volume:2 + description: EFI partition + vendor: Linux + physical id: 3 + bus info: scsi@2:0.0.0,3 + logical name: /dev/sda3 + version: 1.0 + serial: 08c9dedc-878d-4650-a3f8-0e41a6fb1fdb + size: 1GiB + capabilities: extended_attributes large_files ext2 initialized + configuration: filesystem=ext2 label=Gentoo_boot modified=2020-06-27 10:00:47 mounted=2020-06-27 09:26:45 name=Gentoo_boot state=clean + *-volume:3 + description: EFI partition + physical id: 4 + bus info: scsi@2:0.0.0,4 + logical name: /dev/sda4 + serial: 37942d50-6c0b-4aeb-a2f9-056d9963a936 + size: 102GiB + capacity: 102GiB + width: 2532569072 bits + capabilities: encrypted luks initialized + configuration: bits=15417470960 filesystem=luks hash=sha256 version=2 + *-volume:4 + description: EXT4 volume + vendor: Linux + physical id: 5 + bus info: scsi@2:0.0.0,5 + logical name: /dev/sda5 + logical name: / + version: 1.0 + serial: 23cbec55-6ee6-4ec4-9d41-a9f79ee39da7 + size: 93GiB + capabilities: journaled extended_attributes large_files huge_files dir_nlink recover 64bit extents ext4 ext2 initialized + configuration: created=2020-06-13 13:44:46 filesystem=ext4 label=Devuan_root lastmountpoint=/ modified=2021-01-30 00:46:36 mount.fstype=ext4 mount.options=rw,noatime,nodiratime,errors=remount-ro mounted=2021-01-30 00:46:48 name=Devuan_root state=mounted + *-volume:5 + description: Linux swap volume + vendor: Linux + physical id: 6 + bus info: scsi@2:0.0.0,6 + logical name: /dev/sda6 + version: 1 + serial: bca5b558-f37c-40f3-abbb-b5395036a215 + size: 2047MiB + capacity: 2047MiB + capabilities: nofs swap initialized + configuration: filesystem=swap label=Swap2G pagesize=4095 + *-serial + description: SMBus + product: NM10/ICH7 Family SMBus Controller + vendor: Intel Corporation + physical id: 1f.3 + bus info: pci@0000:00:1f.3 + version: 01 + width: 32 bits + clock: 33MHz + configuration: driver=i801_smbus latency=0 + resources: irq:19 ioport:500(size=32) + *-pnp00:00 + product: PnP device PNP0c02 + physical id: 1 + capabilities: pnp + configuration: driver=system + *-pnp00:01 + product: PnP device PNP0b00 + physical id: 2 + capabilities: pnp + configuration: driver=rtc_cmos + *-pnp00:02 + product: PnP device PNP0c02 + physical id: 3 + capabilities: pnp + configuration: driver=system + *-pnp00:03 + product: PnP device PNP0c02 + physical id: 5 + capabilities: pnp + configuration: driver=system + *-pnp00:04 + product: PnP device PNP0c01 + physical id: 6 + capabilities: pnp + configuration: driver=system diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3260f73..3f849fc 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -56,6 +56,7 @@ ## Gigabyte +- [GA-G41M-ES2L](gigabyte/ga-g41m-es2l.md) - [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md) ## HP diff --git a/configs/config.gigabyte_ga-g41m-es2l b/configs/config.gigabyte_ga-g41m-es2l new file mode 100644 index 0000000..817ddf8 --- /dev/null +++ b/configs/config.gigabyte_ga-g41m-es2l @@ -0,0 +1,9 @@ +CONFIG_VENDOR_GIGABYTE=y +CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_PAYLOAD_CONFIGFILE=".config_seabios" +CONFIG_USE_OPTION_TABLE=y +CONFIG_USE_BLOBS=y +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +CONFIG_REALTEK_8168_MACADDRESS="6c:f0:49:a3:e3:d5" -- To view, visit https://review.coreboot.org/c/coreboot/+/50368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib45cfea15b43d7399e9d209f7ba7c6b24fe860dd Gerrit-Change-Number: 50368 Gerrit-PatchSet: 1 Gerrit-Owner: Alexey Vazhnov <vazhnov(a)boot-keys.org> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021