Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50338 )
Change subject: soc/amd/cezanne/romstage: Store early dram region
......................................................................
soc/amd/cezanne/romstage: Store early dram region
Needed so we can reserve the memory.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50338
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/amd/cezanne/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
Angel Pons: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index c7e7e5c..773c6a9 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <amdblocks/memmap.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <console/uart.h>
@@ -33,5 +34,7 @@
fsp_memory_init(acpi_is_wakeup_s3());
+ memmap_stash_early_dram_usage();
+
run_ramstage();
}
--
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50338 )
Change subject: soc/amd/cezanne/romstage: Store early dram region
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50338/comment/225a507d_d2c69f19
PS1, Line 9: Needed so we can reserve the memory
> nit: missing a period at the end of the sentence
Done
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Felix Held has uploaded a new patch set (#2) to the change originally created by Raul Rangel. ( https://review.coreboot.org/c/coreboot/+/50338 )
Change subject: soc/amd/cezanne/romstage: Store early dram region
......................................................................
soc/amd/cezanne/romstage: Store early dram region
Needed so we can reserve the memory.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5
---
M src/soc/amd/cezanne/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/50338/2
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50337 )
Change subject: soc/amd/picasso: Move memmap_early_dram to common blocks
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/memmap.h:
https://review.coreboot.org/c/coreboot/+/50337/comment/3ea9e5e4_3c2a5d4a
PS1, Line 13: uint32_t size;
> I wonder if these should be `uintptr_t base` and `size_t size`
yeah, that would avoid some casts. since this patch is about moving things around, it's probably something that should be done as a follow-up; will look into it
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50283 )
Change subject: mb/google/zork: update telemetry settings for dirinboz
......................................................................
Patch Set 3: Code-Review+1
(2 comments)
Patchset:
PS3:
> The -25 seems odd to me, but that's what the bug specifies, so LGTM.
we probably should make that field in chip.h a signed integer then; but that's out of scope for this patch
PS3:
> Huh, telemetry settings improve performance? Now that's magic! […]
i think the telemetry thing is between the soc and the step down converter. but yes, i also wondered about that name when i started working on the project. maybe something we should look into for cezanne, since renaming this for picasso would probably not be worth the hassle. i hope that i'll remember that when we're at the point where we add that code for cezanne. maybe that prefix was chosen to be consistent with the reference code though
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