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Change subject: soc/amd/common/memmap: use proper type in memmap_early_dram struct
......................................................................
Patch Set 1: Code-Review-1
(1 comment)
File src/soc/amd/common/block/include/amdblocks/memmap.h:
https://review.coreboot.org/c/coreboot/+/50370/comment/409a0315_ce85563b
PS1, Line 12: uintptr_t base;
> At one point anything ending up in CBMEM was expected to use fixed width fields. […]
good point.
on some other patch, i wanted to use resource_t for either this or something similar, but got pushback against that. don't remember the reasoning behind that though
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Change subject: nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Since it's not a new change, 24h have already elapsed. Submitting to fix master.
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Hello build bot (Jenkins), Nico Huber, Damien Zammit, Arthur Heymans, Patrick Rudolph, Michael Büchler,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49388
to look at the new patch set (#2).
Change subject: nb/intel/x4x: Correct DDR3 turnaround table
......................................................................
nb/intel/x4x: Correct DDR3 turnaround table
Comparing against MRC, looks like the values for TA3 and TA4 are
backwards. All of them. Thus, correct the tables accordingly.
Tested on Acer G43T-AM3, DDR3-1066 and CL = 8 now works.
Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4
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Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/northbridge/intel/x4x/raminit_ddr23.c
1 file changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/49388/2
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Change subject: [TESTME] nb/intel/x4x: Correct DDR3 turnaround table
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I tested this with RAM sticks specified for DDR3-1066 with CAS latency (tCL) 7. […]
Thanks for testing!
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Change subject: [TESTME] nb/intel/x4x: Correct DDR3 turnaround table
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
I tested this with RAM sticks specified for DDR3-1066 with CAS latency (tCL) 7. Coreboot was tricked into using CL = 8 instead, as suggested on IRC. Without this change boot fails. With this change everything works including suspend/resume.
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Change subject: nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors
......................................................................
Patch Set 5: Code-Review+2
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