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Change subject: nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
So I submitted CB:50169 out-of-order and now master is broken. This patch fixes the breakage.
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Change subject: soc/amd/common/memmap: use proper type in memmap_early_dram struct
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/memmap.h:
https://review.coreboot.org/c/coreboot/+/50370/comment/0a7b1335_0afd8515
PS1, Line 12: uintptr_t base;
At one point anything ending up in CBMEM was expected to use fixed width fields. This is probably related to speculations of having i386 romstage and x86_64 ramstage.
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Change subject: nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors
......................................................................
nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.
Change-Id: If6d6cba76bdd1134372ab2faa475e574fdc5fddf
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---
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/acpi/i945.asl
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/i945.h
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5 files changed, 21 insertions(+), 35 deletions(-)
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Change subject: nb/intel/x4x: Use common {DMI,EP,MCH}BAR accessors
......................................................................
nb/intel/x4x: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.
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M src/northbridge/intel/x4x/memmap.h
M src/northbridge/intel/x4x/x4x.h
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Change subject: nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessors
......................................................................
nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.
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5 files changed, 19 insertions(+), 38 deletions(-)
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Change subject: nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessors
......................................................................
nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
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Change subject: nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessors
......................................................................
nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessors
Drop unused sandybridge.h includes to avoid build failures on Ironlake.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
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M src/mainboard/asus/p8z77-m_pro/early_init.c
M src/mainboard/dell/optiplex_9010/early_init.c
M src/mainboard/google/butterfly/early_init.c
M src/mainboard/google/link/early_init.c
M src/mainboard/google/parrot/early_init.c
M src/mainboard/google/stout/early_init.c
M src/mainboard/intel/dcp847ske/romstage.c
M src/mainboard/intel/emeraldlake2/early_init.c
M src/mainboard/kontron/ktqm77/early_init.c
M src/mainboard/lenovo/x220/early_init.c
M src/mainboard/roda/rv11/variants/rv11/early_init.c
M src/mainboard/roda/rv11/variants/rw11/early_init.c
M src/mainboard/samsung/lumpy/early_init.c
M src/mainboard/samsung/stumpy/early_init.c
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/early_init.c
M src/northbridge/intel/sandybridge/memmap.h
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/sandybridge/sandybridge.h
M src/southbridge/intel/bd82x6x/early_rcba.c
M src/southbridge/intel/bd82x6x/early_usb.c
M src/southbridge/intel/ibexpeak/early_usb.c
22 files changed, 61 insertions(+), 69 deletions(-)
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Change subject: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
......................................................................
nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42
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---
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/haswell/acpi/ctdp.asl
M src/northbridge/intel/haswell/acpi/hostbridge.asl
M src/northbridge/intel/haswell/early_init.c
M src/northbridge/intel/haswell/haswell.h
M src/northbridge/intel/haswell/memmap.h
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/romstage.c
8 files changed, 29 insertions(+), 31 deletions(-)
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50292 )
Change subject: soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option
......................................................................
soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option
No board in tree selects a different base address, so this can be
removed from Kconfig and be treated like the other base addresses in the
I/O space that are defines in iomap.h.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Iec3d4476e3a6a5d2b226edef4c41f503a0c81f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50292
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/include/soc/iomap.h
2 files changed, 1 insertion(+), 8 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index baf3f4e..b400e1b 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -250,13 +250,6 @@
Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.
-config STONEYRIDGE_ACPI_IO_BASE
- hex
- default 0x400
- help
- Base address for the ACPI registers.
- This value must match the hardcoded value of AGESA.
-
config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL
hex
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index 92d99e4..d8befbe 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -27,7 +27,7 @@
/* I/O Ranges */
#define ACPI_SMI_CTL_PORT 0xb2
-#define ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE
+#define ACPI_IO_BASE 0x400
#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */
#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */
#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */
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