Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50307 )
Change subject: Apply locked MSR check to all BDW-DE platforms
......................................................................
Apply locked MSR check to all BDW-DE platforms
It was initially applied to Wedge100 and MonoLake in CB:30290
and the issue has now been observed on Watson as well.
Original change: [CB:30290][commit 817994c1be]
Signed-off-by: Deomid "rojer" Ryabkov <rojer9(a)fb.com>
Change-Id: Ica9557ff159321abed55f9402aee626f18fe526b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50307
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/ocp/monolake/romstage.c
M src/mainboard/ocp/wedge100s/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
3 files changed, 22 insertions(+), 39 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c
index ef41b77..ebc43de 100644
--- a/src/mainboard/ocp/monolake/romstage.c
+++ b/src/mainboard/ocp/monolake/romstage.c
@@ -19,9 +19,6 @@
#include <soc/romstage.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <drivers/vpd/vpd.h>
-#include <cpu/x86/msr.h>
-#include <cf9_reset.h>
-#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/lpc.h>
@@ -193,20 +190,7 @@
*/
void early_mainboard_romstage_entry(void)
{
- /*
- * Sometimes the system boots in an invalid state, where random values
- * have been written to MSRs and then the MSRs are locked.
- * Seems to always happen on warm reset.
- *
- * Power cycling or a board_reset() isn't sufficient in this case, so
- * issue a full_reset() to "fix" this issue.
- */
- msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
- if (msr.lo & 1) {
- console_init();
- printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
- full_reset();
- }
+
}
/**
diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c
index 108d7a1..b1f8f26 100644
--- a/src/mainboard/ocp/wedge100s/romstage.c
+++ b/src/mainboard/ocp/wedge100s/romstage.c
@@ -17,9 +17,6 @@
#include <stddef.h>
#include <soc/romstage.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
-#include <cpu/x86/msr.h>
-#include <cf9_reset.h>
-#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/lpc.h>
@@ -44,25 +41,6 @@
if (CONFIG(CONSOLE_SERIAL))
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
-
- /*
- * Sometimes the system boots in an invalid state, where random values
- * have been written to MSRs and then the MSRs are locked.
- * Seems to always happen on warm reset.
- *
- * Power cycling or a board_reset() isn't sufficient in this case, so
- * issue a full_reset() to "fix" this issue.
- *
- * It seems to be a deficiency in the reset logic, as other
- * FSP broadwell DE boards are not affected.
- */
- msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
- if (msr.lo & 1) {
- console_init();
- printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
- full_reset();
- }
}
/**
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 9699927..dbf4bc3 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -21,8 +21,10 @@
#include <cbmem.h>
#include <console/console.h>
#include <console/usb.h>
+#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cf9_reset.h>
#include <program_loading.h>
#include <timestamp.h>
#include <version.h>
@@ -125,7 +127,24 @@
iio_hide(dev);
}
}
+}
+static void check_msr_lock(void)
+{
+ /*
+ * Sometimes the system boots in an invalid state, where random values
+ * have been written to MSRs and then the MSRs are locked.
+ * Seems to always happen on warm reset.
+ *
+ * Power cycling or a board_reset() isn't sufficient in this case, so
+ * issue a full_reset() to "fix" this issue.
+ */
+ msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
+ if (msr.lo & 1) {
+ console_init();
+ printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
+ full_reset();
+ }
}
/* Entry from cache-as-ram.inc. */
@@ -146,6 +165,8 @@
enable_integrated_uart(CONFIG_UART_FOR_CONSOLE);
}
+ check_msr_lock();
+
/* Call into mainboard. */
post_code(0x41);
early_mainboard_romstage_entry();
--
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Gerrit-Project: coreboot
Gerrit-Branch: 4.11_branch
Gerrit-Change-Id: Ica9557ff159321abed55f9402aee626f18fe526b
Gerrit-Change-Number: 50307
Gerrit-PatchSet: 8
Gerrit-Owner: Deomid "rojer" Ryabkov <rojer9(a)fb.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com>
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50306 )
Change subject: util/autoport: Fix a typo in readme.md
......................................................................
util/autoport: Fix a typo in readme.md
Change-Id: Ifa1e751354c644e2ad9613253b90eb5db0a1f043
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50306
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M util/autoport/readme.md
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
diff --git a/util/autoport/readme.md b/util/autoport/readme.md
index f2b2697..907d600 100644
--- a/util/autoport/readme.md
+++ b/util/autoport/readme.md
@@ -269,7 +269,7 @@
* If they use different data, use several files.
If memory initialization is not working, in particular write training (timB)
-on DIMM's second rank fails, try enbling rank 1 mirroring, which can't be
+on DIMM's second rank fails, try enabling rank 1 mirroring, which can't be
detected by inteltool. It is described by SPD field "Address Mapping from Edge
Connector to DRAM", byte `63` (`0x3f`). Bit 0 describes Rank 1 Mapping,
0 = standard, 1 = mirrored; set it to 1. Bits 1-7 are reserved.
--
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50361 )
Change subject: soc/intel/braswell,skylake: Drop logo parameters from devicetree
......................................................................
Patch Set 1: Code-Review+2
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50370 )
Change subject: soc/amd/common/memmap: add comment about types in memmap_early_dram
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/memmap.h:
https://review.coreboot.org/c/coreboot/+/50370/comment/47494716_afc9dee4
PS2, Line 12: /* fixed size types, so the layout in CBFS won't change for 32 vs. 64 bit stages */
CBMEM
Also the comment is starting to like a complete sentence.
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