Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49402 )
Change subject: nb/intel/x4x: Update write leveling comment
......................................................................
nb/intel/x4x: Update write leveling comment
Fix a typo and do some style improvements.
Change-Id: Ibc7e1869faa6b9ae12a51b1c3d209bbd8e54b0d2
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49402
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
---
M src/northbridge/intel/x4x/dq_dqs.c
1 file changed, 9 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index 4722dfe..0a65165 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -746,19 +746,19 @@
* DDR3 uses flyby topology where the clock signal takes a different path
* than the data signal, to allow for better signal intergrity.
* Therefore the delay on the data signals needs to account for this.
- * This is done by sampleling the DQS write (tx) signal back over
- * the DQ signal and looking for delay values where the sample transitions
+ * This is done by sampling the DQS write (tx) signal back over the DQ
+ * signal and looking for delay values where the sample transitions
* from high to low.
* Here the following is done:
- * - enable write levelling on the first populated rank
- * - disable output on other populated ranks
- * - start from safe DQS (tx) delays (other transitions can be
- * found at different starting values but are generally bad)
+ * - Enable write levelling on the first populated rank.
+ * - Disable output on other populated ranks.
+ * - Start from safe DQS (tx) delays. Other transitions can be
+ * found at different starting values but are generally bad.
* - loop0: decrease DQS (tx) delays until low is sampled,
* loop1: increase DQS (tx) delays until high is sampled,
- * That way we are sure to hit a low-high transition
- * - put all ranks in normal mode of operation again
- * - note: All ranks need to be leveled together
+ * This way, we are sure to have hit a low-high transition.
+ * - Put all ranks in normal mode of operation again.
+ * Note: All ranks need to be leveled together.
*/
void search_write_leveling(struct sysinfo *s)
{
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49402 )
Change subject: nb/intel/x4x: Update write leveling comment
......................................................................
Patch Set 3: Code-Review+2
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Change subject: superio/aspeed: setup early serial for AST2600
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Patch Set 1:
This change is ready for review.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49402 )
Change subject: nb/intel/x4x: Update write leveling comment
......................................................................
Patch Set 3:
(1 comment)
File src/northbridge/intel/x4x/dq_dqs.c:
https://review.coreboot.org/c/coreboot/+/49402/comment/dd0ae83d_c9220381
PS2, Line 749: * This is done by by sampling the the DQS write (tx) signal back over
> Nit: `by` and `the` are doubled
Thanks, done.
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Change subject: nb/intel/x4x: Update write leveling comment
......................................................................
Patch Set 2:
(1 comment)
File src/northbridge/intel/x4x/dq_dqs.c:
https://review.coreboot.org/c/coreboot/+/49402/comment/397af0d2_0390d0c6
PS2, Line 749: * This is done by by sampling the the DQS write (tx) signal back over
Nit: `by` and `the` are doubled
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Hello build bot (Jenkins), Damien Zammit, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49402
to look at the new patch set (#2).
Change subject: nb/intel/x4x: Update write leveling comment
......................................................................
nb/intel/x4x: Update write leveling comment
Fix a typo and do some style improvements.
Change-Id: Ibc7e1869faa6b9ae12a51b1c3d209bbd8e54b0d2
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/northbridge/intel/x4x/dq_dqs.c
1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/49402/2
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50370 )
Change subject: soc/amd/common/memmap: add comment about types in memmap_early_dram
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/memmap.h:
https://review.coreboot.org/c/coreboot/+/50370/comment/71c2b006_cc2ad628
PS2, Line 12: /* fixed size types, so the layout in CBFS won't change for 32 vs. 64 bit stages */
> CBMEM […]
oh, you're right. yeah, it's a half-sentence so it's clear what it's about, but still fits into the 96 chars
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