coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/common/memmap: add comment about types in memmap_early_dram
by Felix Held (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50370 to look at the new patch set (#3). Change subject: soc/amd/common/memmap: add comment about types in memmap_early_dram ...................................................................... soc/amd/common/memmap: add comment about types in memmap_early_dram Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reported-by: Angel Pons <th3fanbus(a)gmail.com> Change-Id: I295bfcb05571492adbe81ffc579a835be4abffe1 --- M src/soc/amd/common/block/include/amdblocks/memmap.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/50370/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I295bfcb05571492adbe81ffc579a835be4abffe1 Gerrit-Change-Number: 50370 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/x4x: Constify DDR2 ODT table
by Patrick Georgi (Code Review) 07 Feb '21

07 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49401 ) Change subject: nb/intel/x4x: Constify DDR2 ODT table ...................................................................... nb/intel/x4x: Constify DDR2 ODT table Change-Id: Id5b5dc584ab93620ae58cf43fe0d47015d512f82 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49401 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 61e9e9d..16e257f 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1146,7 +1146,7 @@ static void program_odt(struct sysinfo *s) { u8 i; - static u16 ddr2_odt[16][2] = { + static const u16 ddr2_odt[16][2] = { { 0x0000, 0x0000 }, /* NC_NC */ { 0x0000, 0x0001 }, /* x8SS_NC */ { 0x0000, 0x0011 }, /* x8DS_NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b5dc584ab93620ae58cf43fe0d47015d512f82 Gerrit-Change-Number: 49401 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x: Clean up RCOMP cosmetics
by Patrick Georgi (Code Review) 07 Feb '21

07 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49400 ) Change subject: nb/intel/x4x: Clean up RCOMP cosmetics ...................................................................... nb/intel/x4x: Clean up RCOMP cosmetics Clean up cosmetics after refactoring the code. Reflow long lines and align values in the tables, and also remove a now-unnecessary scope. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I2712c1ad5404d6968d18d762e6048c5da120ff78 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49400 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 31 insertions(+), 49 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 9734caa..61e9e9d 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1037,9 +1037,9 @@ static void prog_rcomp(struct sysinfo *s) { u8 i, j, k, reg8; - const u32 ddr2_x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A, - 0x04040404, 0x08070605, 0x0C0B0A09, 0x100F0E0D }; - const u16 ddr2_x378[5] = { 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777 }; + const u32 ddr2_x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0d0c0b0a, + 0x04040404, 0x08070605, 0x0c0b0a09, 0x100f0e0d }; + const u16 ddr2_x378[5] = { 0xaaaa, 0x7777, 0x7777, 0x7777, 0x7777 }; const u32 ddr2_x382[5] = { 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 }; const u32 ddr2_x386[5] = { 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 }; const u32 ddr2_x38a[5] = { 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 }; @@ -1049,24 +1049,24 @@ const u32 ddr2_x39a[5] = { 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 }; const u32 ddr2_x39e[5] = { 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 }; - const u32 ddr3_x32a[8] = {0x06060606, 0x06060606, 0x0b090807, 0x12110f0d, - 0x06060606, 0x08070606, 0x0d0b0a09, 0x16161511}; - const u16 ddr3_x378[5] = {0xbbbb, 0x6666, 0x6666, 0x6666, 0x6666}; - const u32 ddr3_x382[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; - const u32 ddr3_x386[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; - const u32 ddr3_x38a[5] = {0x06060605, 0x07060504, 0x07060504, 0x34343434, 0x34343434}; - const u32 ddr3_x38e[5] = {0x09080707, 0x09090808, 0x09090808, 0x34343434, 0x34343434}; - const u32 ddr3_x392[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; - const u32 ddr3_x396[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; - const u32 ddr3_x39a[5] = {0x07060606, 0x08070605, 0x08070605, 0x34343434, 0x34343434}; - const u32 ddr3_x39e[5] = {0x09090807, 0x0b0b0a09, 0x0b0b0a09, 0x34343434, 0x34343434}; + const u32 ddr3_x32a[8] = { 0x06060606, 0x06060606, 0x0b090807, 0x12110f0d, + 0x06060606, 0x08070606, 0x0d0b0a09, 0x16161511 }; + const u16 ddr3_x378[5] = { 0xbbbb, 0x6666, 0x6666, 0x6666, 0x6666 }; + const u32 ddr3_x382[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; + const u32 ddr3_x386[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; + const u32 ddr3_x38a[5] = { 0x06060605, 0x07060504, 0x07060504, 0x34343434, 0x34343434 }; + const u32 ddr3_x38e[5] = { 0x09080707, 0x09090808, 0x09090808, 0x34343434, 0x34343434 }; + const u32 ddr3_x392[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; + const u32 ddr3_x396[5] = { 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434 }; + const u32 ddr3_x39a[5] = { 0x07060606, 0x08070605, 0x08070605, 0x34343434, 0x34343434 }; + const u32 ddr3_x39e[5] = { 0x09090807, 0x0b0b0a09, 0x0b0b0a09, 0x34343434, 0x34343434 }; const u16 *x378; const u32 *x32a, *x382, *x386, *x38a, *x38e; const u32 *x392, *x396, *x39a, *x39e; const u16 addr[5] = { 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c }; - u8 bit[5] = { 0, 1, 1, 0, 0 }; + const u8 bit[5] = { 0, 1, 1, 0, 0 }; if (s->spd_type == DDR2) { x32a = ddr2_x32a; @@ -1094,50 +1094,32 @@ FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { /* RCOMP data group is special, program it separately */ - MCHBAR32_AND_OR(0x400*i + 0x31c, ~0xff000, - 0xaa000); - MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff, - 0x6666); + MCHBAR32_AND_OR(0x400*i + 0x31c, ~0xff000, 0xaa000); + MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff, 0x6666); for (k = 0; k < 8; k++) { - MCHBAR32_AND_OR(0x400*i + 0x31c + - 0xe + (k << 2), - ~0x3f3f3f3f, x32a[k]); - MCHBAR32_AND_OR(0x400*i + 0x31c + - 0x2e + (k << 2), - ~0x3f3f3f3f, x32a[k]); + MCHBAR32_AND_OR(0x400*i + 0x32a + (k << 2), ~0x3f3f3f3f, x32a[k]); + MCHBAR32_AND_OR(0x400*i + 0x34a + (k << 2), ~0x3f3f3f3f, x32a[k]); } MCHBAR8_AND_OR(0x400*i + 0x31c, ~1, 0); /* Now program the other RCOMP groups */ for (j = 0; j < ARRAY_SIZE(addr); j++) { - { - MCHBAR16_AND_OR(0x400*i + addr[j], - ~0xf000, 0xa000); - MCHBAR16_AND_OR(0x400*i + addr[j] + 4, - ~0xffff, x378[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0xe, - ~0x3f3f3f3f, x382[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x12, - ~0x3f3f3f3f, x386[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x16, - ~0x3f3f3f3f, x38a[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1a, - ~0x3f3f3f3f, x38e[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1e, - ~0x3f3f3f3f, x392[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x22, - ~0x3f3f3f3f, x396[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x26, - ~0x3f3f3f3f, x39a[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, - ~0x3f3f3f3f, x39e[j]); - } + MCHBAR16_AND_OR(0x400*i + addr[j] + 0, ~0xf000, 0xa000); + MCHBAR16_AND_OR(0x400*i + addr[j] + 4, ~0xffff, x378[j]); + + MCHBAR32_AND_OR(0x400*i + addr[j] + 0x0e, ~0x3f3f3f3f, x382[j]); + MCHBAR32_AND_OR(0x400*i + addr[j] + 0x12, ~0x3f3f3f3f, x386[j]); + MCHBAR32_AND_OR(0x400*i + addr[j] + 0x16, ~0x3f3f3f3f, x38a[j]); + MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1a, ~0x3f3f3f3f, x38e[j]); + MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1e, ~0x3f3f3f3f, x392[j]); + MCHBAR32_AND_OR(0x400*i + addr[j] + 0x22, ~0x3f3f3f3f, x396[j]); + MCHBAR32_AND_OR(0x400*i + addr[j] + 0x26, ~0x3f3f3f3f, x39a[j]); + MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, ~0x3f3f3f3f, x39e[j]); /* Override command group strength multiplier */ if (s->spd_type == DDR3 && BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { - MCHBAR16_AND_OR(0x378 + 0x400 * i, - ~0xffff, 0xcccc); + MCHBAR16_AND_OR(0x378 + 0x400 * i, ~0xffff, 0xcccc); } MCHBAR8_AND_OR(0x400*i + addr[j], ~1, bit[j]); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2712c1ad5404d6968d18d762e6048c5da120ff78 Gerrit-Change-Number: 49400 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x: Drop unused first array index
by Patrick Georgi (Code Review) 07 Feb '21

07 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49399 ) Change subject: nb/intel/x4x: Drop unused first array index ...................................................................... nb/intel/x4x: Drop unused first array index The first RCOMP group (data) is programmed differently, and has its own tables. Remove the unused first index from the other tables, and adjust the loop bound accordingly. Cosmetics are cleaned up in a follow-up. Tested on Asus P5QL PRO (DDR2), still boots. Change-Id: I3010acbd00f762c91aebeaf1625ed7543b14bf74 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49399 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 22 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 06570c2..9734caa 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1039,34 +1039,34 @@ u8 i, j, k, reg8; const u32 ddr2_x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A, 0x04040404, 0x08070605, 0x0C0B0A09, 0x100F0E0D }; - const u16 ddr2_x378[6] = { 0, 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777 }; - const u32 ddr2_x382[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 }; - const u32 ddr2_x386[6] = { 0, 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 }; - const u32 ddr2_x38a[6] = { 0, 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 }; - const u32 ddr2_x38e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 }; - const u32 ddr2_x392[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 }; - const u32 ddr2_x396[6] = { 0, 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 }; - const u32 ddr2_x39a[6] = { 0, 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 }; - const u32 ddr2_x39e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 }; + const u16 ddr2_x378[5] = { 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777 }; + const u32 ddr2_x382[5] = { 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 }; + const u32 ddr2_x386[5] = { 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 }; + const u32 ddr2_x38a[5] = { 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 }; + const u32 ddr2_x38e[5] = { 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 }; + const u32 ddr2_x392[5] = { 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 }; + const u32 ddr2_x396[5] = { 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 }; + const u32 ddr2_x39a[5] = { 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 }; + const u32 ddr2_x39e[5] = { 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 }; const u32 ddr3_x32a[8] = {0x06060606, 0x06060606, 0x0b090807, 0x12110f0d, 0x06060606, 0x08070606, 0x0d0b0a09, 0x16161511}; - const u16 ddr3_x378[6] = {0, 0xbbbb, 0x6666, 0x6666, 0x6666, 0x6666}; - const u32 ddr3_x382[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; - const u32 ddr3_x386[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; - const u32 ddr3_x38a[6] = {0, 0x06060605, 0x07060504, 0x07060504, 0x34343434, 0x34343434}; - const u32 ddr3_x38e[6] = {0, 0x09080707, 0x09090808, 0x09090808, 0x34343434, 0x34343434}; - const u32 ddr3_x392[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; - const u32 ddr3_x396[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; - const u32 ddr3_x39a[6] = {0, 0x07060606, 0x08070605, 0x08070605, 0x34343434, 0x34343434}; - const u32 ddr3_x39e[6] = {0, 0x09090807, 0x0b0b0a09, 0x0b0b0a09, 0x34343434, 0x34343434}; + const u16 ddr3_x378[5] = {0xbbbb, 0x6666, 0x6666, 0x6666, 0x6666}; + const u32 ddr3_x382[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; + const u32 ddr3_x386[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; + const u32 ddr3_x38a[5] = {0x06060605, 0x07060504, 0x07060504, 0x34343434, 0x34343434}; + const u32 ddr3_x38e[5] = {0x09080707, 0x09090808, 0x09090808, 0x34343434, 0x34343434}; + const u32 ddr3_x392[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; + const u32 ddr3_x396[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434}; + const u32 ddr3_x39a[5] = {0x07060606, 0x08070605, 0x08070605, 0x34343434, 0x34343434}; + const u32 ddr3_x39e[5] = {0x09090807, 0x0b0b0a09, 0x0b0b0a09, 0x34343434, 0x34343434}; const u16 *x378; const u32 *x32a, *x382, *x386, *x38a, *x38e; const u32 *x392, *x396, *x39a, *x39e; - const u16 addr[6] = { 0x31c, 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c }; - u8 bit[6] = { 0, 0, 1, 1, 0, 0 }; + const u16 addr[5] = { 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c }; + u8 bit[5] = { 0, 1, 1, 0, 0 }; if (s->spd_type == DDR2) { x32a = ddr2_x32a; @@ -1109,10 +1109,8 @@ MCHBAR8_AND_OR(0x400*i + 0x31c, ~1, 0); /* Now program the other RCOMP groups */ - for (j = 0; j < 6; j++) { - if (j == 0) { - continue; - } else { + for (j = 0; j < ARRAY_SIZE(addr); j++) { + { MCHBAR16_AND_OR(0x400*i + addr[j], ~0xf000, 0xa000); MCHBAR16_AND_OR(0x400*i + addr[j] + 4, -- To view, visit https://review.coreboot.org/c/coreboot/+/49399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3010acbd00f762c91aebeaf1625ed7543b14bf74 Gerrit-Change-Number: 49399 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x: Unroll programming RCOMP data group
by Patrick Georgi (Code Review) 07 Feb '21

07 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49398 ) Change subject: nb/intel/x4x: Unroll programming RCOMP data group ...................................................................... nb/intel/x4x: Unroll programming RCOMP data group The RCOMP data group is special and is programmed differently. Prepare to simplify the code by programming it outside of the loop. Subsequent commits will simplify the logic even further, then clean up cosmetics. The special DDR3 case in the loop overwrites the command group strength multiplier value. It doesn't need to be programmed for each RCOMP group. Add a comment to justify not programming this register while programming the settings for the RCOMP data group. Tested on Asus P5QL PRO (DDR2), still boots. Change-Id: I5c2484f48e3c07e8e787b1894932e342e8e8a75c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49398 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 19 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index e466d64..06570c2 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1093,20 +1093,25 @@ } FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + /* RCOMP data group is special, program it separately */ + MCHBAR32_AND_OR(0x400*i + 0x31c, ~0xff000, + 0xaa000); + MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff, + 0x6666); + for (k = 0; k < 8; k++) { + MCHBAR32_AND_OR(0x400*i + 0x31c + + 0xe + (k << 2), + ~0x3f3f3f3f, x32a[k]); + MCHBAR32_AND_OR(0x400*i + 0x31c + + 0x2e + (k << 2), + ~0x3f3f3f3f, x32a[k]); + } + MCHBAR8_AND_OR(0x400*i + 0x31c, ~1, 0); + + /* Now program the other RCOMP groups */ for (j = 0; j < 6; j++) { if (j == 0) { - MCHBAR32_AND_OR(0x400*i + addr[j], ~0xff000, - 0xaa000); - MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff, - 0x6666); - for (k = 0; k < 8; k++) { - MCHBAR32_AND_OR(0x400*i + addr[j] + - 0xe + (k << 2), - ~0x3f3f3f3f, x32a[k]); - MCHBAR32_AND_OR(0x400*i + addr[j] + - 0x2e + (k << 2), - ~0x3f3f3f3f, x32a[k]); - } + continue; } else { MCHBAR16_AND_OR(0x400*i + addr[j], ~0xf000, 0xa000); @@ -1129,6 +1134,8 @@ MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, ~0x3f3f3f3f, x39e[j]); } + + /* Override command group strength multiplier */ if (s->spd_type == DDR3 && BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { MCHBAR16_AND_OR(0x378 + 0x400 * i, -- To view, visit https://review.coreboot.org/c/coreboot/+/49398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c2484f48e3c07e8e787b1894932e342e8e8a75c Gerrit-Change-Number: 49398 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x: Report if running in async mode
by Patrick Georgi (Code Review) 07 Feb '21

07 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49397 ) Change subject: nb/intel/x4x: Report if running in async mode ...................................................................... nb/intel/x4x: Report if running in async mode Change-Id: I84d5457173598e8ff41dfb048a6858b41c5692ac Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49397 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 3741c26..e466d64 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -895,6 +895,7 @@ if (j < 2) { MCHBAR8_AND(0x1c8, ~0x1f); async = 1; + printk(BIOS_NOTICE, "HMC failed, using async mode\n"); } switch (s->selected_timings.mem_clk) { -- To view, visit https://review.coreboot.org/c/coreboot/+/49397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84d5457173598e8ff41dfb048a6858b41c5692ac Gerrit-Change-Number: 49397 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x: Factor out setting Tx DLL tap and PI
by Patrick Georgi (Code Review) 07 Feb '21

07 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49396 ) Change subject: nb/intel/x4x: Factor out setting Tx DLL tap and PI ...................................................................... nb/intel/x4x: Factor out setting Tx DLL tap and PI These settings can be programmed with a single register write. Factor the writes out into a single function to avoid some redundancy. Tested on Asus P5QL PRO, still boots. Change-Id: I3a08c255dd2b0deae650c7fe2ba4e1f4d1cef581 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49396 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 14 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 9fb05b0..3741c26 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -247,14 +247,18 @@ MCHBAR32_OR(0x2c4, 0x100); } +static void write_txdll_tap_pi(u8 ch, u16 reg, u8 tap, u8 pi) +{ + MCHBAR8_AND_OR(0x400 * ch + reg, ~0x7f, pi << 4 | tap); +} + static void clkset0(u8 ch, const struct dll_setting *setting) { MCHBAR16_AND_OR(0x400*ch + 0x5a0, ~0xc440, (setting->clk_delay << 14) | (setting->db_sel << 6) | (setting->db_en << 10)); - MCHBAR8_AND_OR(0x400*ch + 0x581, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x581, ~0xf, setting->tap); + write_txdll_tap_pi(ch, 0x581, setting->tap, setting->pi); } static void clkset1(u8 ch, const struct dll_setting *setting) @@ -263,8 +267,7 @@ (setting->clk_delay << 16) | (setting->db_sel << 7) | (setting->db_en << 11)); - MCHBAR8_AND_OR(0x400*ch + 0x582, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x582, ~0xf, setting->tap); + write_txdll_tap_pi(ch, 0x582, setting->tap, setting->pi); } static void ctrlset0(u8 ch, const struct dll_setting *setting) @@ -273,8 +276,7 @@ (setting->clk_delay << 24) | (setting->db_sel << 20) | (setting->db_en << 21)); - MCHBAR8_AND_OR(0x400*ch + 0x584, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x584, ~0xf, setting->tap); + write_txdll_tap_pi(ch, 0x584, setting->tap, setting->pi); } static void ctrlset1(u8 ch, const struct dll_setting *setting) @@ -283,8 +285,7 @@ (setting->clk_delay << 27) | (setting->db_sel << 22) | (setting->db_en << 23)); - MCHBAR8_AND_OR(0x400*ch + 0x585, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x585, ~0xf, setting->tap); + write_txdll_tap_pi(ch, 0x585, setting->tap, setting->pi); } static void ctrlset2(u8 ch, const struct dll_setting *setting) @@ -298,8 +299,7 @@ (setting->clk_delay << 14) | (setting->db_sel << 12) | (setting->db_en << 13)); - MCHBAR8_AND_OR(0x400*ch + 0x586, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x586, ~0xf, setting->tap); + write_txdll_tap_pi(ch, 0x586, setting->tap, setting->pi); } static void ctrlset3(u8 ch, const struct dll_setting *setting) @@ -313,8 +313,7 @@ (setting->clk_delay << 10) | (setting->db_sel << 8) | (setting->db_en << 9)); - MCHBAR8_AND_OR(0x400*ch + 0x587, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x587, ~0xf, setting->tap); + write_txdll_tap_pi(ch, 0x587, setting->tap, setting->pi); } static void cmdset(u8 ch, const struct dll_setting *setting) @@ -323,8 +322,7 @@ MCHBAR8_AND_OR(0x400*ch + 0x594, ~0x60, (setting->db_sel << 5) | (setting->db_en << 6)); - MCHBAR8_AND_OR(0x400*ch + 0x580, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x580, ~0xf, setting->tap); + write_txdll_tap_pi(ch, 0x580, setting->tap, setting->pi); } /** @@ -347,10 +345,7 @@ ~(0x3 << (16 + lane * 2)), setting->clk_delay << (16+lane * 2)); - MCHBAR8(0x400*ch + 0x520 + lane * 4 + rank) = - (MCHBAR8(0x400*ch + 0x520 + lane * 4) & ~0x7f) | - (setting->pi << 4) | - setting->tap; + write_txdll_tap_pi(ch, 0x520 + lane * 4 + rank, setting->tap, setting->pi); } } @@ -368,8 +363,7 @@ MCHBAR32_AND_OR(0x400 * ch + 0x5c8 + rank * 4, ~(0x3 << (lane * 2)), setting->clk_delay << (2 * lane)); - MCHBAR8_AND_OR(0x400*ch + 0x500 + lane * 4 + rank, ~0x7f, - (setting->pi << 4) | setting->tap); + write_txdll_tap_pi(ch, 0x500 + lane * 4 + rank, setting->tap, setting->pi); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/49396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a08c255dd2b0deae650c7fe2ba4e1f4d1cef581 Gerrit-Change-Number: 49396 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x: Correct ctrlset{2,3} register mask
by Patrick Georgi (Code Review) 07 Feb '21

07 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49391 ) Change subject: nb/intel/x4x: Correct ctrlset{2,3} register mask ...................................................................... nb/intel/x4x: Correct ctrlset{2,3} register mask MRC uses an incorrect mask when programming this register, but the reset default value is zero and it is only programmed once. As it makes no difference, we can safely use the correct mask. Document this difference in a comment to indicate the deviation from MRC behavior is intentional. The default value for this register was dumped from Asus P5QL PRO. Change-Id: I93b0c382f76e141b319414258e40a8bfe6c7848a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49391 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 12 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 119eccd..9fb05b0 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -289,7 +289,12 @@ static void ctrlset2(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000, + /* + * MRC uses an incorrect mask when programming this register, but + * the reset default value is zero and it is only programmed once. + * As it makes no difference, we can safely use the correct mask. + */ + MCHBAR32_AND_OR(0x400*ch + 0x598, ~0xf000, (setting->clk_delay << 14) | (setting->db_sel << 12) | (setting->db_en << 13)); @@ -299,7 +304,12 @@ static void ctrlset3(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000, + /* + * MRC uses an incorrect mask when programming this register, but + * the reset default value is zero and it is only programmed once. + * As it makes no difference, we can safely use the correct mask. + */ + MCHBAR32_AND_OR(0x400*ch + 0x598, ~0xf00, (setting->clk_delay << 10) | (setting->db_sel << 8) | (setting->db_en << 9)); -- To view, visit https://review.coreboot.org/c/coreboot/+/49391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93b0c382f76e141b319414258e40a8bfe6c7848a Gerrit-Change-Number: 49391 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x: Clean up cosmetics of raminit tables
by Patrick Georgi (Code Review) 07 Feb '21

07 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49390 ) Change subject: nb/intel/x4x: Clean up cosmetics of raminit tables ...................................................................... nb/intel/x4x: Clean up cosmetics of raminit tables Consistently use commas after the last element of arrays, and also align columns of values and comments. Remove `MHz` units from DDR speed values to avoid confusion, as the memory's actual clock speed is half of these. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: Id13022483c6221ce87d21dd21a5cfe4317a55ccd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49390 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_tables.c 1 file changed, 200 insertions(+), 177 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index 2ae3c06..b22a77e 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -4,7 +4,7 @@ #include "raminit.h" const struct dll_setting default_ddr2_667_ctrl[7] = { - /* tap pi db delay coarse*/ + /* tap pi db delay coarse */ {13, 0, 1, 0, 0, 0}, /* clkset0 */ {4, 1, 0, 0, 0, 0}, /* ctrl0 */ {13, 0, 1, 0, 0, 0}, /* clkset1 */ @@ -33,7 +33,7 @@ {9, 1, 0, 0, 1, 0}, {6, 4, 0, 0, 1, 0}, {6, 2, 0, 0, 1, 0}, - {5, 4, 0, 0, 1, 0} + {5, 4, 0, 0, 1, 0}, }; const struct dll_setting default_ddr2_800_ctrl[7] = { @@ -66,196 +66,212 @@ {10, 0, 0, 0, 1, 0}, {8, 1, 0, 0, 1, 0}, {7, 5, 0, 0, 1, 0}, - {6, 2, 0, 0, 1, 0} + {6, 2, 0, 0, 1, 0}, }; const struct dll_setting default_ddr3_800_ctrl[2][7] = { { /* 1N */ /* tap pi db(2) delay coarse */ - {8, 2, 0, 0, 0, 0}, - {8, 4, 0, 0, 0, 0}, - {9, 5, 0, 0, 0, 0}, - {6, 1, 0, 0, 0, 0}, - {8, 4, 0, 0, 0, 0}, + {8, 2, 0, 0, 0, 0}, + {8, 4, 0, 0, 0, 0}, + {9, 5, 0, 0, 0, 0}, + {6, 1, 0, 0, 0, 0}, + {8, 4, 0, 0, 0, 0}, {10, 0, 0, 0, 0, 0}, - {10, 0, 0, 0, 0, 0}, }, + {10, 0, 0, 0, 0, 0}, + }, { /* 2N */ - {2, 2, 1, 1, 0, 0}, - {2, 4, 1, 1, 0, 0}, - {3, 5, 0, 0, 0, 0}, - {3, 2, 1, 1, 0, 0}, - {2, 4, 1, 1, 0, 0}, - {3, 6, 0, 0, 0, 0}, - {3, 6, 0, 0, 0, 0}, } + {2, 2, 1, 1, 0, 0}, + {2, 4, 1, 1, 0, 0}, + {3, 5, 0, 0, 0, 0}, + {3, 2, 1, 1, 0, 0}, + {2, 4, 1, 1, 0, 0}, + {3, 6, 0, 0, 0, 0}, + {3, 6, 0, 0, 0, 0}, + }, }; const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES] = { { /* 1N */ {12, 0, 1, 0, 0, 0}, - {1, 1, 1, 1, 1, 0}, - {2, 4, 1, 1, 1, 0}, - {3, 5, 0, 0, 1, 0}, - {4, 3, 0, 0, 1, 0}, - {5, 2, 0, 0, 1, 0}, - {6, 1, 0, 0, 1, 0}, - {6, 4, 0, 0, 1, 0}, }, + {1, 1, 1, 1, 1, 0}, + {2, 4, 1, 1, 1, 0}, + {3, 5, 0, 0, 1, 0}, + {4, 3, 0, 0, 1, 0}, + {5, 2, 0, 0, 1, 0}, + {6, 1, 0, 0, 1, 0}, + {6, 4, 0, 0, 1, 0}, + }, { /* 2N */ - {5, 6, 0, 0, 0, 0}, - {8, 0, 0, 0, 0, 0}, - {9, 4, 0, 0, 0, 0}, + {5, 6, 0, 0, 0, 0}, + {8, 0, 0, 0, 0, 0}, + {9, 4, 0, 0, 0, 0}, {10, 4, 1, 0, 0, 0}, {11, 3, 1, 0, 0, 0}, {12, 1, 1, 0, 0, 0}, - {0, 1, 1, 1, 1, 0}, - {0, 3, 1, 1, 1, 0}, } + {0, 1, 1, 1, 1, 0}, + {0, 3, 1, 1, 1, 0}, + }, }; const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES] = { { /* 1N */ - {4, 1, 0, 0, 1, 0}, - {6, 4, 0, 0, 1, 0}, - {8, 1, 0, 0, 1, 0}, - {8, 6, 0, 0, 1, 0}, - {9, 5, 0, 0, 1, 0}, + {4, 1, 0, 0, 1, 0}, + {6, 4, 0, 0, 1, 0}, + {8, 1, 0, 0, 1, 0}, + {8, 6, 0, 0, 1, 0}, + {9, 5, 0, 0, 1, 0}, {10, 2, 0, 0, 1, 0}, {10, 6, 1, 0, 1, 0}, - {11, 4, 1, 0, 1, 0} }, + {11, 4, 1, 0, 1, 0}, + }, { /* 2N */ {11, 0, 1, 0, 0, 0}, - {0, 3, 1, 1, 1, 0}, - {2, 1, 1, 1, 1, 0}, - {2, 5, 1, 1, 1, 0}, - {3, 5, 0, 0, 1, 0}, - {4, 2, 0, 0, 1, 0}, - {4, 6, 0, 0, 1, 0}, - {5, 4, 0, 0, 1, 0}, } + {0, 3, 1, 1, 1, 0}, + {2, 1, 1, 1, 1, 0}, + {2, 5, 1, 1, 1, 0}, + {3, 5, 0, 0, 1, 0}, + {4, 2, 0, 0, 1, 0}, + {4, 6, 0, 0, 1, 0}, + {5, 4, 0, 0, 1, 0}, + }, }; const struct dll_setting default_ddr3_1067_ctrl[2][7] = { { /* 1N */ - {8, 5, 0, 0, 0, 0}, - {7, 6, 0, 0, 0, 0}, + {8, 5, 0, 0, 0, 0}, + {7, 6, 0, 0, 0, 0}, {10, 2, 1, 0, 0, 0}, - {4, 4, 0, 0, 0, 0}, - {7, 6, 0, 0, 0, 0}, - {9, 2, 1, 0, 0, 0}, - {9, 2, 1, 0, 0, 0}, }, + {4, 4, 0, 0, 0, 0}, + {7, 6, 0, 0, 0, 0}, + {9, 2, 1, 0, 0, 0}, + {9, 2, 1, 0, 0, 0}, + }, { /* 2N */ - {1, 5, 1, 1, 0, 0}, - {0, 6, 1, 1, 0, 0}, - {3, 2, 0, 0, 0, 0}, - {2, 6, 1, 1, 0, 0}, - {0, 6, 1, 1, 0, 0}, - {2, 2, 1, 1, 0, 0}, - {2, 2, 1, 1, 0, 0}, } + {1, 5, 1, 1, 0, 0}, + {0, 6, 1, 1, 0, 0}, + {3, 2, 0, 0, 0, 0}, + {2, 6, 1, 1, 0, 0}, + {0, 6, 1, 1, 0, 0}, + {2, 2, 1, 1, 0, 0}, + {2, 2, 1, 1, 0, 0}, + }, }; const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES] = { { /* 1N */ - {2, 5, 1, 1, 1, 0}, - {5, 1, 0, 0, 1, 0}, - {6, 6, 0, 0, 1, 0}, - {8, 0, 0, 0, 1, 0}, - {8, 6, 0, 0, 1, 0}, - {9, 6, 1, 0, 1, 0}, + {2, 5, 1, 1, 1, 0}, + {5, 1, 0, 0, 1, 0}, + {6, 6, 0, 0, 1, 0}, + {8, 0, 0, 0, 1, 0}, + {8, 6, 0, 0, 1, 0}, + {9, 6, 1, 0, 1, 0}, {10, 6, 1, 0, 1, 0}, - {0, 1, 1, 1, 0, 1}, }, + {0, 1, 1, 1, 0, 1}, + }, { /* 2N */ - {6, 4, 0, 0, 0, 0}, - {9, 1, 1, 0, 0, 0}, + {6, 4, 0, 0, 0, 0}, + {9, 1, 1, 0, 0, 0}, {10, 6, 1, 0, 0, 0}, - {1, 0, 1, 1, 1, 0}, - {1, 6, 1, 1, 1, 0}, - {2, 5, 1, 1, 1, 0}, - {3, 5, 0, 0, 1, 0}, - {4, 1, 0, 0, 1, 0}, - } + {1, 0, 1, 1, 1, 0}, + {1, 6, 1, 1, 1, 0}, + {2, 5, 1, 1, 1, 0}, + {3, 5, 0, 0, 1, 0}, + {4, 1, 0, 0, 1, 0}, + }, }; const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES] = { { /* 1N */ - {6, 5, 0, 0, 1, 0}, - {9, 3, 1, 0, 1, 0}, - {0, 2, 1, 1, 0, 1}, - {1, 0, 1, 1, 0, 1}, - {2, 0, 1, 1, 0, 1}, - {2, 5, 1, 1, 0, 1}, - {3, 2, 0, 0, 0, 1}, - {4, 1, 0, 0, 0, 1}, }, + {6, 5, 0, 0, 1, 0}, + {9, 3, 1, 0, 1, 0}, + {0, 2, 1, 1, 0, 1}, + {1, 0, 1, 1, 0, 1}, + {2, 0, 1, 1, 0, 1}, + {2, 5, 1, 1, 0, 1}, + {3, 2, 0, 0, 0, 1}, + {4, 1, 0, 0, 0, 1}, + }, { /* 2N */ {10, 5, 1, 0, 0, 0}, - {2, 3, 1, 1, 1, 0}, - {4, 1, 0, 0, 1, 0}, - {5, 0, 0, 0, 1, 0}, - {6, 0, 0, 0, 1, 0}, - {6, 5, 0, 0, 1, 0}, - {7, 2, 0, 0, 1, 0}, - {8, 1, 0, 0, 1, 0}, - } + {2, 3, 1, 1, 1, 0}, + {4, 1, 0, 0, 1, 0}, + {5, 0, 0, 0, 1, 0}, + {6, 0, 0, 0, 1, 0}, + {6, 5, 0, 0, 1, 0}, + {7, 2, 0, 0, 1, 0}, + {8, 1, 0, 0, 1, 0}, + }, }; const struct dll_setting default_ddr3_1333_ctrl[2][7] = { { /* 1N */ - {8, 5, 0, 0, 0, 0}, - {9, 0, 1, 0, 0, 0}, + {8, 5, 0, 0, 0, 0}, + {9, 0, 1, 0, 0, 0}, {10, 2, 1, 0, 0, 0}, - {0, 0, 1, 1, 0, 0}, - {9, 0, 1, 0, 0, 0}, + {0, 0, 1, 1, 0, 0}, + {9, 0, 1, 0, 0, 0}, {10, 4, 1, 0, 0, 0}, - {10, 4, 1, 0, 0, 0}, }, + {10, 4, 1, 0, 0, 0}, + }, { /* 2N */ - {1, 6, 1, 1, 0, 0}, - {2, 2, 1, 1, 0, 0}, - {4, 2, 0, 0, 0, 0}, - {3, 1, 1, 1, 0, 0}, - {2, 2, 1, 1, 0, 0}, - {4, 5, 0, 0, 0, 0}, - {4, 5, 0, 0, 0, 0}, } + {1, 6, 1, 1, 0, 0}, + {2, 2, 1, 1, 0, 0}, + {4, 2, 0, 0, 0, 0}, + {3, 1, 1, 1, 0, 0}, + {2, 2, 1, 1, 0, 0}, + {4, 5, 0, 0, 0, 0}, + {4, 5, 0, 0, 0, 0}, + }, }; const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES] = { { /* 1N */ - {2, 4, 1, 1, 1, 0}, - {5, 1, 0, 0, 1, 0}, - {6, 6, 0, 0, 1, 0}, - {8, 0, 0, 0, 1, 0}, - {8, 6, 0, 0, 1, 0}, - {9, 5, 1, 0, 1, 0}, + {2, 4, 1, 1, 1, 0}, + {5, 1, 0, 0, 1, 0}, + {6, 6, 0, 0, 1, 0}, + {8, 0, 0, 0, 1, 0}, + {8, 6, 0, 0, 1, 0}, + {9, 5, 1, 0, 1, 0}, {10, 6, 1, 0, 1, 0}, - {0, 1, 1, 1, 0, 1}, }, + {0, 1, 1, 1, 0, 1}, + }, { /* 2N */ {10, 4, 0, 0, 0, 0}, - {0, 3, 1, 1, 1, 0}, - {3, 2, 1, 1, 1, 0}, - {5, 0, 0, 0, 1, 0}, - {6, 1, 0, 0, 1, 0}, - {7, 4, 0, 0, 1, 0}, - {9, 2, 0, 0, 1, 0}, - {9, 6, 0, 0, 1, 0}, } + {0, 3, 1, 1, 1, 0}, + {3, 2, 1, 1, 1, 0}, + {5, 0, 0, 0, 1, 0}, + {6, 1, 0, 0, 1, 0}, + {7, 4, 0, 0, 1, 0}, + {9, 2, 0, 0, 1, 0}, + {9, 6, 0, 0, 1, 0}, + }, }; const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES] = { { /* 1N */ - {6, 5, 0, 0, 1, 0}, - {9, 3, 1, 0, 1, 0}, - {0, 2, 1, 1, 0, 1}, - {1, 0, 1, 1, 0, 1}, - {2, 0, 1, 1, 0, 1}, - {2, 5, 1, 1, 0, 1}, - {3, 2, 0, 0, 0, 1}, - {4, 1, 0, 0, 0, 1}, }, + {6, 5, 0, 0, 1, 0}, + {9, 3, 1, 0, 1, 0}, + {0, 2, 1, 1, 0, 1}, + {1, 0, 1, 1, 0, 1}, + {2, 0, 1, 1, 0, 1}, + {2, 5, 1, 1, 0, 1}, + {3, 2, 0, 0, 0, 1}, + {4, 1, 0, 0, 0, 1}, + }, { /* 2N */ - {1, 3, 1, 1, 1, 0}, - {5, 6, 0, 0, 1, 0}, - {8, 5, 0, 0, 1, 0}, + {1, 3, 1, 1, 1, 0}, + {5, 6, 0, 0, 1, 0}, + {8, 5, 0, 0, 1, 0}, {10, 2, 0, 0, 1, 0}, {11, 1, 0, 0, 1, 0}, {12, 3, 1, 0, 1, 0}, {13, 6, 1, 0, 1, 0}, - {0, 3, 1, 1, 0, 1}, } + {0, 3, 1, 1, 0, 1}, + }, }; -const u8 ddr3_emrs1_rtt_nom_config[16][4] = { /* [Config][Rank] */ +const u8 ddr3_emrs1_rtt_nom_config[16][4] = { /* [Config][Rank] */ {0x00, 0x00, 0x00, 0x00}, /* NC_NC */ {0x11, 0x00, 0x00, 0x00}, /* 8S_NC */ {0x11, 0x11, 0x00, 0x00}, /* 8D_NC */ @@ -274,35 +290,38 @@ {0x81, 0x00, 0x81, 0x00}, /* 16S_16S */ }; -const u8 post_jedec_tab[3][4][2]= /* [FSB][DDR freq][17:13 or 12:8] */ -{ /* FSB DDR */ - {{0x3, 0x5}, /* 800 667 */ - {0x3, 0x4}, /* 800 800 */ +const u8 post_jedec_tab[3][4][2] = { /* [FSB][DDR freq][17:13 or 12:8] */ + { /* FSB DDR */ + {0x3, 0x5}, /* 800 667 */ + {0x3, 0x4}, /* 800 800 */ }, - {{0x4, 0x8}, /* 1067 667 */ - {0x4, 0x6}, /* 1067 800 */ - {0x3, 0x5}, /* 1067 1066 */ + { + {0x4, 0x8}, /* 1067 667 */ + {0x4, 0x6}, /* 1067 800 */ + {0x3, 0x5}, /* 1067 1066 */ }, - {{0x5, 0x9}, /* 1333 667 */ - {0x4, 0x7}, /* 1333 800 */ - {0x4, 0x7}, /* 1333 1066 */ - {0x4, 0x7} /* 1333 1333 */ + { + {0x5, 0x9}, /* 1333 667 */ + {0x4, 0x7}, /* 1333 800 */ + {0x4, 0x7}, /* 1333 1066 */ + {0x4, 0x7}, /* 1333 1333 */ }, }; const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */ /* 115h[15:0] 117h[23:0] */ { /* 1N mode */ - { /* DDR3 800MHz */ + { /* DDR3 800 */ {0x0189, 0x000aaa}, /* CAS = 5 */ {0x0189, 0x101aaa}, /* CAS = 6 */ }, - { /* DDR3 1067MHz */ + { /* DDR3 1067 */ {0x0000, 0x000000}, /* CAS = 5 - Not supported */ {0x0089, 0x000bbb}, /* CAS = 6 */ {0x0099, 0x101bbb}, /* CAS = 7 */ - {0x0099, 0x202bbb} /* CAS = 8 */ - },{ /* DDR3 1333 */ + {0x0099, 0x202bbb}, /* CAS = 8 */ + }, + { /* DDR3 1333 */ {0x0000, 0x000000}, /* CAS = 5 - Not supported */ {0x0000, 0x000000}, /* CAS = 6 - Not supported */ {0x0000, 0x000000}, /* CAS = 7 - Not supported */ @@ -312,61 +331,65 @@ }, }, { /* 2N mode */ - { /* DDR3 800MHz */ + { /* DDR3 800 */ {0x0189, 0x000aaa}, /* CAS = 5 */ {0x0189, 0x101aaa}, /* CAS = 6 */ - {0x0000, 0x000000}, /* CAS = 7 - Not supported */ - {0x0000, 0x000000} /* CAS = 8 - Not supported */ }, { /* DDR3 1067 */ {0x0000, 0x000000}, /* CAS = 5 - Not supported */ {0x0089, 0x000bbb}, /* CAS = 6 */ {0x0099, 0x101bbb}, /* CAS = 7 */ - {0x0099, 0x202bbb} /* CAS = 8 */ - },{ /* DDR3 1333MHz */ - {0x0000, 0x000000}, /* CAS = 5 - Not supported */ + {0x0099, 0x202bbb}, /* CAS = 8 */ + }, + { /* DDR3 1333 */ + {0x0000, 0x000000}, /* CAS = 5 - Not supported */ {0x0000, 0x000000}, /* CAS = 6 - Not supported */ {0x0000, 0x000000}, /* CAS = 7 - Not supported */ {0x019a, 0x0078dc}, /* CAS = 8 */ {0x019a, 0x1088dc}, /* CAS = 9 */ {0x019a, 0x2098dc}, /* CAS = 10 */ }, - } + }, }; const u8 ddr3_c2_x264[3][6] = { /* [freq][cas] */ - /* DDR3 800MHz */ - {0x78, /* CAS = 5 */ - 0x89}, /* CAS = 6 */ - /* DDR3 1066 */ - {0x00, /* CAS = 5 - Not supported */ - 0xff, /* CAS = 6 */ - 0x8a, /* CAS = 7 */ - 0x9a}, /* CAS = 8 */ - /* DDR3 1333 */ - {0x00, /* CAS = 5 - Not supported */ - 0x00, /* CAS = 6 - Not supported */ - 0xff, /* CAS = 7 - Not supported */ - 0xff, /* CAS = 8 */ - 0xff, /* CAS = 9 */ - 0xff}, /* CAS = 10 */ + { /* DDR3 800 */ + 0x78, /* CAS = 5 */ + 0x89, /* CAS = 6 */ + }, + { /* DDR3 1066 */ + 0x00, /* CAS = 5 - Not supported */ + 0xff, /* CAS = 6 */ + 0x8a, /* CAS = 7 */ + 0x9a, /* CAS = 8 */ + }, + { /* DDR3 1333 */ + 0x00, /* CAS = 5 - Not supported */ + 0x00, /* CAS = 6 - Not supported */ + 0xff, /* CAS = 7 - Not supported */ + 0xff, /* CAS = 8 */ + 0xff, /* CAS = 9 */ + 0xff, /* CAS = 10 */ + }, }; const u16 ddr3_c2_x23c[3][6]={ /* [freq][cas] */ - /* DDR3 800MHz */ - {0x9bbb, /* CAS = 5 */ - 0x8bbb}, /* CAS = 6 */ - /* DDR3 1066MHz */ - {0x0000, /* CAS = 5 - Not supported */ - 0x9baa, /* CAS = 6 */ - 0x8caa, /* CAS = 7 */ - 0x7daa}, /* CAS = 8 */ - - /* DDR3 1333MHz */ - {0x0000, /* CAS = 5 - Not supported */ - 0x0000, /* CAS = 6 - Not supported */ - 0x0000, /* CAS = 7 - Not supported */ - 0xaecb, /* CAS = 8 */ - 0x9fcb, /* CAS = 9 */ - 0x8fcb}, /* CAS = 10 */ + { /* DDR3 800 */ + 0x9bbb, /* CAS = 5 */ + 0x8bbb, /* CAS = 6 */ + }, + { /* DDR3 1066 */ + 0x0000, /* CAS = 5 - Not supported */ + 0x9baa, /* CAS = 6 */ + 0x8caa, /* CAS = 7 */ + 0x7daa, /* CAS = 8 */ + }, + { /* DDR3 1333 */ + 0x0000, /* CAS = 5 - Not supported */ + 0x0000, /* CAS = 6 - Not supported */ + 0x0000, /* CAS = 7 - Not supported */ + 0xaecb, /* CAS = 8 */ + 0x9fcb, /* CAS = 9 */ + 0x8fcb, /* CAS = 10 */ + }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/49390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id13022483c6221ce87d21dd21a5cfe4317a55ccd Gerrit-Change-Number: 49390 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x: Drop commented-out statement
by Patrick Georgi (Code Review) 07 Feb '21

07 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49389 ) Change subject: nb/intel/x4x: Drop commented-out statement ...................................................................... nb/intel/x4x: Drop commented-out statement Time has proven this statement to be unnecessary. Uncommenting it would not have any effect on the existing code, thus remove it completely. Change-Id: Iff4cdd71435e4fd69d4f3284e9fb2830fdd5b173 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49389 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index fc39a5d..119eccd 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -776,8 +776,6 @@ ~rank2clken[r + i * 4]); } } - - //reg8 = 0x00; // FIXME don't switch on all clocks anyway } /* END EACH CHANNEL */ if (s->spd_type == DDR2) { -- To view, visit https://review.coreboot.org/c/coreboot/+/49389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff4cdd71435e4fd69d4f3284e9fb2830fdd5b173 Gerrit-Change-Number: 49389 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit February 2021