coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

1 participants
7192 discussions

Change in coreboot[master]: doc/mb/ocp: Update DeltaLake for a VPD variable used in LinuxBoot
by Johnny Lin (Code Review) 08 Feb '21

08 Feb '21

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50377 ) Change subject: doc/mb/ocp: Update DeltaLake for a VPD variable used in LinuxBoot ...................................................................... doc/mb/ocp: Update DeltaLake for a VPD variable used in LinuxBoot Change-Id: I3da7291188ee06c50008aa3fc7142210215044d4 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M Documentation/mainboard/ocp/deltalake.md 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/50377/1 diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index 9ef2357..4cf4a24 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -58,6 +58,8 @@ VPD variables supported are: - firmware_version: This variable holds overall firmware version. coreboot uses that value to populate smbios type 1 version field. +- bmc_bootorder_override: When it's set to 1 IPMI OEM command can override boot + order. The boot order override is done in the u-root LinuxBoot payload. - DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. ## Working features -- To view, visit https://review.coreboot.org/c/coreboot/+/50377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3da7291188ee06c50008aa3fc7142210215044d4 Gerrit-Change-Number: 50377 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/{baytrail,broadwell}: Add missing <cbmem.h>
by Felix Held (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: Angel Pons, Patrick Rudolph, HAOUAS Elyes. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50375 ) Change subject: soc/intel/{baytrail,broadwell}: Add missing <cbmem.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4e55f8233e5cb5cea575ad0581adf457a45ba9a Gerrit-Change-Number: 50375 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 07 Feb 2021 23:37:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sb/intel/common/rtc.c: Define __SIMPLE_DEVICE__
by Angel Pons (Code Review) 07 Feb '21

07 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50376 ) Change subject: sb/intel/common/rtc.c: Define __SIMPLE_DEVICE__ ...................................................................... sb/intel/common/rtc.c: Define __SIMPLE_DEVICE__ Change-Id: Ie11fffdf907227ab315bfd4887aaa5de3602bd24 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/rtc.c 1 file changed, 3 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/50376/1 diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c index 63fc124..ef30d9a5 100644 --- a/src/southbridge/intel/common/rtc.c +++ b/src/southbridge/intel/common/rtc.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#define __SIMPLE_DEVICE__ + #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -9,17 +11,11 @@ #include "pmutil.h" #include "rtc.h" -/* PCI Configuration Space (D31:F0): LPC */ -#if defined(__SIMPLE_DEVICE__) #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) -#else -#define PCH_LPC_DEV pcidev_on_root(0x1f, 0) -#endif int rtc_failure(void) { - return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3) - & RTC_BATTERY_DEAD); + return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3) & RTC_BATTERY_DEAD); } void sb_rtc_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/50376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie11fffdf907227ab315bfd4887aaa5de3602bd24 Gerrit-Change-Number: 50376 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/{baytrail,broadwell}: Add missing <cbmem.h>
by Kyösti Mälkki (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: Angel Pons, Patrick Rudolph, HAOUAS Elyes. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50375 ) Change subject: soc/intel/{baytrail,broadwell}: Add missing <cbmem.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4e55f8233e5cb5cea575ad0581adf457a45ba9a Gerrit-Change-Number: 50375 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 07 Feb 2021 23:25:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP] sb/intel/bd82x6x: Support ME Software Disable Mode
by Evgeny Zinoviev (Code Review) 07 Feb '21

07 Feb '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37115 ) Change subject: [WIP] sb/intel/bd82x6x: Support ME Software Disable Mode ...................................................................... [WIP] sb/intel/bd82x6x: Support ME Software Disable Mode AFAIK, ME is supposed to enter Software Temp Disable Mode on the next reboot after receiving the disable command. But my tests on X230 (ME firmware 8.1.1416.40) show that CF9 reset doesn't help here and user must manually perform power off/power on cycle. So for now working algorithm to disable ME is as follows: - run `nvramtool -w me_disable=Enable` - reboot - power off - power on - run `intelmetool -m` to verify that ME is in soft temp disable mode. To enable ME: - run `nvramtool -m me_disable=Disable` - reboot TODO: if it's possible, find a way to perform correct program reset so that user wouldn't have to do one more power off/power on. Change-Id: Ic01526c9731cbef4e8552bbc352133a2415787c2 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/lenovo/x230/cmos.default M src/mainboard/lenovo/x230/cmos.layout M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 5 files changed, 104 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/37115/1 diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default index 979f132..75f27df 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -14,3 +14,4 @@ trackpoint=Enable backlight=Both usb_always_on=Disable +me_disable=Disable diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 27197fb..755d98b 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -73,6 +73,9 @@ # coreboot config options: cpu #424 8 r 0 unused +424 1 e 1 me_disable +425 1 r 0 me_disable_prev +#426 6 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index f82ed3e..41ca3f6 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -23,6 +23,7 @@ #include <halt.h> #include <string.h> #include <timestamp.h> +#include <option.h> #include "me.h" #include "pch.h" @@ -236,7 +237,6 @@ printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24); printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28); - /* Return the requested BIOS action */ printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", me_ack_values[(hfs & 0xe) >> 1]); diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 203d0c0..e05a178 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -185,6 +185,11 @@ #define MKHI_GLOBAL_RESET 0x0b #define MKHI_FWCAPS_GET_RULE 0x02 +#define MKHI_FWCAPS_SET_RULE 0x03 + +#define MKHI_HMRFPO_ENABLE 0x01 +#define MKHI_HMRFPO_LOCK 0x02 +#define MKHI_HMRFPO_DISABLE 0x04 #define MKHI_MDES_ENABLE 0x09 diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f13ced9..5d57e02 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -23,6 +23,7 @@ */ #include <arch/acpi.h> +#include <cf9_reset.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> @@ -30,6 +31,7 @@ #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> +#include <pc80/mc146818rtc.h> #include <string.h> #include <delay.h> #include <elog.h> @@ -189,7 +191,7 @@ } static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data) + void *req_data, bool wait_ready) { struct mei_csr host; unsigned int ndata, n; @@ -247,8 +249,11 @@ host.interrupt_generate = 1; write_host_csr(&host); - /* Make sure ME is ready after sending request data */ - return mei_wait_for_me_ready(); + if (!wait_ready) + return 0; + else + /* Make sure ME is ready after sending request data */ + return mei_wait_for_me_ready(); } static int mei_recv_msg(struct mkhi_header *mkhi, @@ -338,10 +343,12 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data, void *rsp_data, int rsp_bytes) { - if (mei_send_msg(mei, mkhi, req_data) < 0) + if (mei_send_msg(mei, mkhi, req_data, true) < 0) return -1; + if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0) return -1; + return 0; } @@ -513,6 +520,50 @@ } #else /* !__SIMPLE_DEVICE__ */ +static void reset(void) { + struct device *lpc = pcidev_on_root(0x1f, 0); + u32 etr3 = pci_read_config32(lpc, ETR3); + u8 cf9; + + etr3 |= ETR3_CF9GR; + pci_write_config32(lpc, ETR3, etr3); + + cf9 = inb(0xcf9); + cf9 |= 0x0e; + outb(cf9, 0xcf9); + + halt(); +} + +static void enable_soft_temp_disable_mode(void) { + u32 message[2] = { 0x06, 0x01 }; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_FWCAPS, + .command = MKHI_FWCAPS_SET_RULE, + }; + struct mei_header mei = { + .is_complete = 1, + .length = sizeof(mkhi) + sizeof(message), + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + }; + + printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + + /* + * ME stops responding after receiving the disable command, + * therefore it makes no sence to wait for it + */ + bool wait_ready = false; + + if (mei_send_msg(&mei, &mkhi, &message, wait_ready) < 0) + printk(BIOS_DEBUG, "ME: %s: me_send_msg returned -1 (wait timeout)\n", + __FUNCTION__); +} + +static void disable_soft_temp_disable_mode(struct device *dev) { + pci_write_config32(dev, PCI_ME_H_GS, 0x20000000); +} /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -675,10 +726,19 @@ { me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; + u8 me_disable, me_disable_prev; + bool need_reset = false; + struct me_hfs hfs; /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); + get_option(&me_disable, "me_disable"); + get_option(&me_disable_prev, "me_disable_prev"); + + printk(BIOS_DEBUG, "ME: me_disable=%u, me_disable_prev=%u\n", + me_disable, me_disable_prev); + switch (path) { case ME_S3WAKE_BIOS_PATH: intel_me_hide(dev); @@ -710,6 +770,17 @@ } #endif + /* Put ME in Software Temporary Disable Mode, if needed */ + if (me_disable) { + printk(BIOS_DEBUG, "ME: need to disable ME\n"); + enable_soft_temp_disable_mode(); + if (!me_disable_prev) { + printk(BIOS_DEBUG, "ME: me_disable_prev differs, need to reset\n"); + need_reset = true; + break; + } + } + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { me_print_fw_version(&mbp_data.fw_version_name); me_print_fwcaps(&mbp_data.fw_caps_sku); @@ -721,12 +792,30 @@ */ break; + case ME_DISABLE_BIOS_PATH: + /* Bring ME out of Softwate Temporary Disable mode, if needed */ + pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + if (hfs.operation_mode == ME_HFS_MODE_DIS && !me_disable) { + printk(BIOS_DEBUG, "ME: need to undisable ME\n"); + disable_soft_temp_disable_mode(dev); + if (me_disable_prev) { + printk(BIOS_DEBUG, "ME: me_disable_prev differs, need to reset\n"); + need_reset = true; + } + } + break; + case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } + + if (me_disable != me_disable_prev) + set_option("me_disable_prev", &me_disable); + + if (need_reset) + reset(); } static struct pci_operations pci_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/37115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic01526c9731cbef4e8552bbc352133a2415787c2 Gerrit-Change-Number: 37115 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

7 60

Change in coreboot[master]: sb/intel: Extract `set_global_reset` function
by Angel Pons (Code Review) 07 Feb '21

07 Feb '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50362 ) Change subject: sb/intel: Extract `set_global_reset` function ...................................................................... sb/intel: Extract `set_global_reset` function To avoid duplicating this function in ramstage, factor it out. Change-Id: I64c59a01ca153770481c28ae404a5dfe8c5382d2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50362 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Evgeny Zinoviev <me(a)ch1p.io> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/early_me_mrc.c M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/me.c A src/southbridge/intel/common/me.h M src/southbridge/intel/ibexpeak/Kconfig 8 files changed, 50 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Evgeny Zinoviev: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index e3ad885..812b6c0 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -18,6 +18,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select SOUTHBRIDGE_INTEL_COMMON_ME select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 6320d2e..09e5f39 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -7,6 +7,7 @@ #include <delay.h> #include <device/pci_def.h> #include <halt.h> +#include <southbridge/intel/common/me.h> #include <string.h> #include <timestamp.h> #include "me.h" @@ -91,22 +92,6 @@ return 0; } -static inline void set_global_reset(int enable) -{ - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); - - /* Clear CF9 Without Resume Well Reset Enable */ - etr3 &= ~ETR3_CWORWRE; - - /* CF9GR indicates a Global Reset */ - if (enable) - etr3 |= ETR3_CF9GR; - else - etr3 &= ~ETR3_CF9GR; - - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); -} - int intel_early_me_init_done(u8 status) { u8 reset, errorcode, opmode; diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c index 0b11fd0..180e466 100644 --- a/src/southbridge/intel/bd82x6x/early_me_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c @@ -6,6 +6,7 @@ #include <delay.h> #include <device/pci_def.h> #include <halt.h> +#include <southbridge/intel/common/me.h> #include <string.h> #include "me.h" #include "pch.h" @@ -96,22 +97,6 @@ return 0; } -static inline void set_global_reset(int enable) -{ - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); - - /* Clear CF9 Without Resume Well Reset Enable */ - etr3 &= ~ETR3_CWORWRE; - - /* CF9GR indicates a Global Reset */ - if (enable) - etr3 |= ETR3_CF9GR; - else - etr3 &= ~ETR3_CF9GR; - - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); -} - int intel_early_me_init_done(u8 status) { u8 reset; diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 1bdefd4..5d7a4ee 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -15,6 +15,9 @@ config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n +config SOUTHBRIDGE_INTEL_COMMON_ME + def_bool n + config SOUTHBRIDGE_INTEL_COMMON_HPET def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index f11ffa6..adacc25 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -7,6 +7,8 @@ all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET) += hpet.c +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME) += me.c + romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c diff --git a/src/southbridge/intel/common/me.c b/src/southbridge/intel/common/me.c new file mode 100644 index 0000000..d495087 --- /dev/null +++ b/src/southbridge/intel/common/me.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <device/pci_ops.h> +#include <types.h> + +#include "me.h" + +#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) + +#define ETR3 0xac +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) +#define ETR3_CF9LOCK (1 << 31) + +void set_global_reset(const bool enable) +{ + u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); + + /* Clear CF9 Without Resume Well Reset Enable */ + etr3 &= ~ETR3_CWORWRE; + + /* CF9GR indicates a Global Reset */ + if (enable) + etr3 |= ETR3_CF9GR; + else + etr3 &= ~ETR3_CF9GR; + + pci_write_config32(PCH_LPC_DEV, ETR3, etr3); +} diff --git a/src/southbridge/intel/common/me.h b/src/southbridge/intel/common/me.h new file mode 100644 index 0000000..81c1b47 --- /dev/null +++ b/src/southbridge/intel/common/me.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_HPET_H +#define SOUTHBRIDGE_INTEL_COMMON_HPET_H + +#include <types.h> + +void set_global_reset(const bool enable); + +#endif /* SOUTHBRIDGE_INTEL_COMMON_HPET_H */ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 34ae2f1..18f7770 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -21,6 +21,7 @@ select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_ME select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC -- To view, visit https://review.coreboot.org/c/coreboot/+/50362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64c59a01ca153770481c28ae404a5dfe8c5382d2 Gerrit-Change-Number: 50362 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: security/tpm/tss/vendor/cr50/cr50.c: Fix typo
by Angel Pons (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: Christian Walter, HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50372 ) Change subject: security/tpm/tss/vendor/cr50/cr50.c: Fix typo ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71c0b3b28979053b73f22f280ff11ba19ee0eee2 Gerrit-Change-Number: 50372 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 07 Feb 2021 22:47:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/{baytrail,broadwell}: Add missing <cbmem.h>
by Patrick Georgi (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: Angel Pons, Patrick Rudolph, HAOUAS Elyes. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50375 ) Change subject: soc/intel/{baytrail,broadwell}: Add missing <cbmem.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4e55f8233e5cb5cea575ad0581adf457a45ba9a Gerrit-Change-Number: 50375 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 07 Feb 2021 22:44:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src: Remove unused <cbmem.h>
by Angel Pons (Code Review) 07 Feb '21

07 Feb '21

Attention is currently required from: HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50182 ) Change subject: src: Remove unused <cbmem.h> ...................................................................... Patch Set 3: (2 comments) File src/soc/intel/baytrail/refcode.c: https://review.coreboot.org/c/coreboot/+/50182/comment/a58990f7_b39b88d0 PS3, Line 30: CBMEM_ID_REFCODE > um CB:50375 File src/soc/intel/broadwell/refcode.c: https://review.coreboot.org/c/coreboot/+/50182/comment/bcf763dd_dc85f157 PS3, Line 26: CBMEM_ID_REFCODE > um CB:50375 -- To view, visit https://review.coreboot.org/c/coreboot/+/50182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e Gerrit-Change-Number: 50182 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 07 Feb 2021 22:43:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/{baytrail,broadwell}: Add missing <cbmem.h>
by Angel Pons (Code Review) 07 Feb '21

07 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50375 ) Change subject: soc/intel/{baytrail,broadwell}: Add missing <cbmem.h> ...................................................................... soc/intel/{baytrail,broadwell}: Add missing <cbmem.h> Change-Id: Ic4e55f8233e5cb5cea575ad0581adf457a45ba9a Fixes: commit 0322bc5ed8 (src: Remove unused <cbmem.h>) Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/refcode.c M src/soc/intel/broadwell/refcode.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/50375/1 diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index d8623ae..8cd7336 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <cbmem.h> #include <console/console.h> #include <console/streams.h> #include <cpu/x86/tsc.h> diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 5d3ccce..31d6ad8 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -2,6 +2,7 @@ #include <string.h> #include <acpi/acpi.h> +#include <cbmem.h> #include <console/console.h> #include <console/streams.h> #include <program_loading.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4e55f8233e5cb5cea575ad0581adf457a45ba9a Gerrit-Change-Number: 50375 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2021