coreboot-gerrit February 2021

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Change in coreboot[master]: nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors
by HAOUAS Elyes (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49756 ) Change subject: nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d6cba76bdd1134372ab2faa475e574fdc5fddf Gerrit-Change-Number: 49756 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 06:18:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/memmap: add comment about types in memmap_early_dram
by Kyösti Mälkki (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50370 ) Change subject: soc/amd/common/memmap: add comment about types in memmap_early_dram ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I295bfcb05571492adbe81ffc579a835be4abffe1 Gerrit-Change-Number: 50370 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Feb 2021 04:59:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell,skylake: Drop logo parameters from devicetree
by Kyösti Mälkki (Code Review) 08 Feb '21

08 Feb '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50361 ) Change subject: soc/intel/braswell,skylake: Drop logo parameters from devicetree ...................................................................... soc/intel/braswell,skylake: Drop logo parameters from devicetree We can never pass memory location of dynamically loaded BMP files in the static devicetree. The parameters passed to FSP are filled at runtime. Change-Id: Ib835ec0d9349ec96d5635e228063f2b7000b70fd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50361 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/chip.h M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 4 files changed, 0 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index d759602..af274ac 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -120,8 +120,6 @@ params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort; params->PcdPcieRootPortSpeed = 0; params->PcdPchSsicEnable = config->PcdPchSsicEnable; - params->PcdLogoPtr = config->PcdLogoPtr; - params->PcdLogoSize = config->PcdLogoSize; params->PcdRtcLock = 0; params->PMIC_I2CBus = config->PMIC_I2CBus; params->ISPEnable = config->ISPEnable; diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index c27ee49..732d73b 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -131,8 +131,6 @@ uint8_t PcdPchUsbSsicPort; uint8_t PcdPchUsbHsicPort; uint8_t PcdPchSsicEnable; - uint32_t PcdLogoPtr; - uint32_t PcdLogoSize; uint8_t PMIC_I2CBus; uint8_t ISPEnable; uint8_t ISPPciDevConfig; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 5b05dd2..88f432d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -256,9 +256,6 @@ dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); params->Heci3Enabled = dev && dev->enabled; - params->LogoPtr = config->LogoPtr; - params->LogoSize = config->LogoSize; - params->CpuConfig.Bits.VmxEnable = CONFIG(ENABLE_VMX); params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index e5592b4..bef0f12 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -288,14 +288,6 @@ u8 SkipExtGfxScan; u8 ScanExtGfxForLegacyOpRom; - /* - * The following fields come from fsp_vpd.h - * These are configuration values that are passed to FSP during - * SiliconInit. - */ - u32 LogoPtr; - u32 LogoSize; - /* GPIO IRQ Route The valid values is 14 or 15*/ u8 GpioIrqSelect; /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/50361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib835ec0d9349ec96d5635e228063f2b7000b70fd Gerrit-Change-Number: 50361 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Drop CID1 from GNVS
by Kyösti Mälkki (Code Review) 08 Feb '21

08 Feb '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50297 ) Change subject: soc/intel: Drop CID1 from GNVS ...................................................................... soc/intel: Drop CID1 from GNVS The only reference to CID1 is in common/acpi/wifi.asl and only two braswell boards include it. Everywhere else the value in GNVS was unused. Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50297 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c 11 files changed, 4 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 9800563..1536de1 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -20,7 +20,6 @@ #include <soc/systemagent.h> #include <string.h> #include <types.h> -#include <wrdd.h> /* * List of supported C-states in this processor. @@ -278,9 +277,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 37fe216..5b09b48 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -18,7 +18,6 @@ #include <soc/pm.h> #include <soc/systemagent.h> #include <string.h> -#include <wrdd.h> #include "chip.h" @@ -182,9 +181,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 18852d4..d9ecfb3 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -20,7 +20,7 @@ DPTE, 8, // 0x1c - Enable DPTF NHLA, 64, // 0x1d - 0x24 NHLT Address NHLL, 32, // 0x25 - 0x28 NHLT Length - CID1, 16, // 0x29 - 0x2a Wifi Country Identifier + , 16, // 0x29 - 0x2a Wifi Country Identifier U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index abc3400..cba60f6 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -20,7 +20,7 @@ u8 dpte; /* 0x1c - Enable DPTF */ u64 nhla; /* 0x1d - 0x24 NHLT Address */ u32 nhll; /* 0x25 - 0x28 NHLT Length */ - u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */ + u16 unused_was_cid1; /* 0x29 - 0x2a Wifi Country Identifier */ u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ u8 uior; /* 0x2f - UART debug controller init on S3 resume */ diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index ba64c04..0c87cfd 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -19,7 +19,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <string.h> -#include <wrdd.h> /* * List of supported C-states in this processor. @@ -246,9 +245,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 67b7ca5..6240f68 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -16,7 +16,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <string.h> -#include <wrdd.h> /* * List of supported C-states in this processor. @@ -177,9 +176,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index a3c2b25..1a9286a 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -19,7 +19,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <string.h> -#include <wrdd.h> /* * List of supported C-states in this processor. @@ -273,9 +272,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 63fda66..10ce77e 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -29,7 +29,6 @@ #include <soc/systemagent.h> #include <string.h> #include <types.h> -#include <wrdd.h> #include <device/pci_ops.h> #include "chip.h" @@ -166,9 +165,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index d5b2c20..1ae61fd 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -37,7 +37,7 @@ DPTE, 8, // 0x30 - Enable DPTF NHLA, 64, // 0x31 - NHLT Address NHLL, 32, // 0x39 - NHLT Length - CID1, 16, // 0x3d - Wifi Country Identifier + , 16, // 0x3d - Wifi Country Identifier U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap UIOR, 8, // 0x42 - UART debug controller init on S3 resume diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 39271d3..2141518 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -37,7 +37,7 @@ u8 dpte; /* 0x30 - Enable DPTF */ u64 nhla; /* 0x31 - NHLT Address */ u32 nhll; /* 0x39 - NHLT Length */ - u16 cid1; /* 0x3d - Wifi Country Identifier */ + u16 unused_was_cid1; /* 0x3d - Wifi Country Identifier */ u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */ u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */ u8 uior; /* 0x42 - UART debug controller init on S3 resume */ diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index f3e821f..d81efb9 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -19,7 +19,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <string.h> -#include <wrdd.h> /* * List of supported C-states in this processor. @@ -273,9 +272,6 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; - /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); - /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; -- To view, visit https://review.coreboot.org/c/coreboot/+/50297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba Gerrit-Change-Number: 50297 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Guard TRAP method in ASL
by Kyösti Mälkki (Code Review) 08 Feb '21

08 Feb '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50358 ) Change subject: soc/intel: Guard TRAP method in ASL ...................................................................... soc/intel: Guard TRAP method in ASL Needed to support build with ACPI_SOC_NVS=n as SMIF object inside GNVS disappears then. Change-Id: Ib798187c24996b74d6345080f7d48c3f657eb512 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50358 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/acpi/platform.asl 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index b1dda02..342a4ef 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -17,6 +17,7 @@ DBG0, 8 } +#if CONFIG(ACPI_SOC_NVS) /* SMI I/O Trap */ Method(TRAP, 1, Serialized) { @@ -24,6 +25,7 @@ TRP0 = 0 // Generate trap Return (SMIF) // Return value of SMI handler } +#endif /* ACPI_SOC_NVS */ /* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. -- To view, visit https://review.coreboot.org/c/coreboot/+/50358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib798187c24996b74d6345080f7d48c3f657eb512 Gerrit-Change-Number: 50358 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Drop CID1 from GNVS
by Kyösti Mälkki (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Lance Zhao, Furquan Shaikh, Subrata Banik, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50297 ) Change subject: soc/intel: Drop CID1 from GNVS ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/include/intelblocks/nvs.h: https://review.coreboot.org/c/coreboot/+/50297/comment/90c7c006_08d0ed83 PS2, Line 23: unused_was_cid1 > But the structure is defined and used within coreboot, there's no 3rdparty dependency. […] And once you notice the offsets appear in the comments, the workload just explodes. About half of the GNVS is still nonsense. -- To view, visit https://review.coreboot.org/c/coreboot/+/50297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba Gerrit-Change-Number: 50297 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 04:13:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/variants/vilboz: Disable ASPM L1.2 for SD card reader
by Dtrain Hsu (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Frank Wu, John Su, Shirley Her, Martin Roth, Furquan Shaikh, Kangheui Won, Rob Barnes, chris wang. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50280 ) Change subject: mb/google/zork/variants/vilboz: Disable ASPM L1.2 for SD card reader ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50280/comment/5a3d5a9e_fa3efe9c PS3, Line 7: Diasable > Disable Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f24c08411eabb1579c76aaafbe3eb054db54f69 Gerrit-Change-Number: 50280 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Shirley Her <shirley.her(a)bayhubtech.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Shirley Her <shirley.her(a)bayhubtech.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 03:04:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/variants/vilboz: Disable ASPM L1.2 for SD card reader
by Dtrain Hsu (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: John Su, Shirley Her, Martin Roth, Furquan Shaikh, Kangheui Won, Rob Barnes, chris wang. Dtrain Hsu has uploaded a new patch set (#4) to the change originally created by John Su. ( https://review.coreboot.org/c/coreboot/+/50280 ) Change subject: mb/google/zork/variants/vilboz: Disable ASPM L1.2 for SD card reader ...................................................................... mb/google/zork/variants/vilboz: Disable ASPM L1.2 for SD card reader From bayhub vendor feedback, OZ711LV2 only set to L1.1 for AMD project, because the reason is AMD’s L1.2 capability is not good causing device lost in past experience, so vilboz need set L1.1 in RC and device both side. BUG=b:177955523 BRANCH=zork TEST=check PCIE_L1_PM_SUB_CNTL 0x378[3:0]=0xA Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I2f24c08411eabb1579c76aaafbe3eb054db54f69 --- M src/mainboard/google/zork/variants/vilboz/variant.c 1 file changed, 47 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/50280/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f24c08411eabb1579c76aaafbe3eb054db54f69 Gerrit-Change-Number: 50280 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Shirley Her <shirley.her(a)bayhubtech.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Shirley Her <shirley.her(a)bayhubtech.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Drop CID1 from GNVS
by Lance Zhao (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Kyösti Mälkki, Patrick Rudolph. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50297 ) Change subject: soc/intel: Drop CID1 from GNVS ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/include/intelblocks/nvs.h: https://review.coreboot.org/c/coreboot/+/50297/comment/38617acc_73830070 PS2, Line 23: unused_was_cid1 > Removing these fields would affect the layout of the structure, and the comments would need to be up […] But the structure is defined and used within coreboot, there's no 3rdparty dependency. so shall be safe to do so right? But fail build as a fail-safe protection make some sense, what about a follow up commit to totally drop it? -- To view, visit https://review.coreboot.org/c/coreboot/+/50297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba Gerrit-Change-Number: 50297 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 02:52:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/variants/vilboz: Diasable ASPM L1.2 for SD card reader
by Frank Wu (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: John Su, Shirley Her, Martin Roth, Furquan Shaikh, Kangheui Won, Rob Barnes, chris wang. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50280 ) Change subject: mb/google/zork/variants/vilboz: Diasable ASPM L1.2 for SD card reader ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50280/comment/23056e3d_157b46ba PS3, Line 7: Diasable Disable -- To view, visit https://review.coreboot.org/c/coreboot/+/50280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f24c08411eabb1579c76aaafbe3eb054db54f69 Gerrit-Change-Number: 50280 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Shirley Her <shirley.her(a)bayhubtech.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Shirley Her <shirley.her(a)bayhubtech.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 02:32:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2021