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Change in coreboot[master]: sb/intel/bd82x6x: Deduplicate ME finalization function
by Angel Pons (Code Review) 06 Feb '21

06 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42050 ) Change subject: sb/intel/bd82x6x: Deduplicate ME finalization function ...................................................................... sb/intel/bd82x6x: Deduplicate ME finalization function Both functions are identical, so we might as well drop one copy. Change-Id: Ifd24f01dab2b5a6b7d154a8e2b1a69c233a0e727 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c 4 files changed, 39 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42050/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index d2a3480..7910623 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -111,57 +111,20 @@ #ifdef __SIMPLE_DEVICE__ -static void intel_me7_finalize_smm(void) -{ - struct me_hfs hfs; - u32 reg32; - u16 reg16; - - update_mei_base_address(); - - /* S3 path will have hidden this device already */ - if (!is_mei_base_address_valid()) - return; - - /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); -} - void intel_me_finalize_smm(void) { u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); switch (did) { case 0x1c3a8086: - intel_me7_finalize_smm(); - break; case 0x1e3a8086: - intel_me8_finalize_smm(); + me_finalize_smm(); break; default: printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); } } -#else +#else /* !__SIMPLE_DEVICE__ */ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index a55a1f2..8fee899 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -245,6 +245,7 @@ int mkhi_end_of_post(void); void update_mei_base_address(void); bool is_mei_base_address_valid(void); +void me_finalize_smm(void); int intel_mei_setup(struct device *dev); int intel_me_extend_valid(struct device *dev); void intel_me_hide(struct device *dev); @@ -258,7 +259,6 @@ int intel_early_me_init_done(u8 status); void intel_me_finalize_smm(void); -void intel_me8_finalize_smm(void); typedef struct { u32 major_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 1a331e9..78f2817 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -99,44 +99,7 @@ print_cap("Wireless LAN (WLAN)", cap->wlan); } -#ifdef __SIMPLE_DEVICE__ - -void intel_me8_finalize_smm(void) -{ - struct me_hfs hfs; - u32 reg32; - u16 reg16; - - update_mei_base_address(); - - /* S3 path will have hidden this device already */ - if (!is_mei_base_address_valid()) - return; - - /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); -} - -#else /* !__SIMPLE_DEVICE__ */ +#ifndef __SIMPLE_DEVICE__ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 83e7fe6..9088d44 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -361,6 +361,41 @@ return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } +void me_finalize_smm(void) +{ + struct me_hfs hfs; + u32 reg32; + u16 reg16; + + update_mei_base_address(); + + /* S3 path will have hidden this device already */ + if (!is_mei_base_address_valid()) + return; + + /* Make sure ME is in a mode that expects EOP */ + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); + memcpy(&hfs, &reg32, sizeof(u32)); + + /* Abort and leave device alone if not normal mode */ + if (hfs.fpt_bad || + hfs.working_state != ME_HFS_CWS_NORMAL || + hfs.operation_mode != ME_HFS_MODE_NORMAL) + return; + + /* Try to send EOP command so ME stops accepting other commands */ + mkhi_end_of_post(); + + /* Make sure IO is disabled */ + reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); + + /* Hide the PCI device */ + RCBA32_OR(FD2, PCH_DISABLE_MEI1); +} + #else /* Prepare ME for MEI messages */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd24f01dab2b5a6b7d154a8e2b1a69c233a0e727 Gerrit-Change-Number: 42050 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: sb/intel/bd82x6x: Relocate intel_me_finalize_smm()
by Angel Pons (Code Review) 06 Feb '21

06 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42051 ) Change subject: sb/intel/bd82x6x: Relocate intel_me_finalize_smm() ...................................................................... sb/intel/bd82x6x: Relocate intel_me_finalize_smm() This allows us to reduce the scope of three functions. Change-Id: Ib08c0eb4b01e10aa38efac434ff23a488e9e2787 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_common.c 3 files changed, 18 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42051/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7910623..dd3ecd7 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -109,22 +109,7 @@ return 0; } -#ifdef __SIMPLE_DEVICE__ - -void intel_me_finalize_smm(void) -{ - u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); - switch (did) { - case 0x1c3a8086: - case 0x1e3a8086: - me_finalize_smm(); - break; - default: - printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); - } -} - -#else /* !__SIMPLE_DEVICE__ */ +#ifndef __SIMPLE_DEVICE__ /* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 8fee899..29d5749 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -243,9 +243,7 @@ void *req_data, void *rsp_data, int rsp_bytes); int mkhi_end_of_post(void); -void update_mei_base_address(void); -bool is_mei_base_address_valid(void); -void me_finalize_smm(void); +void intel_me_finalize_smm(void); int intel_mei_setup(struct device *dev); int intel_me_extend_valid(struct device *dev); void intel_me_hide(struct device *dev); @@ -258,8 +256,6 @@ int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); -void intel_me_finalize_smm(void); - typedef struct { u32 major_version : 16; u32 minor_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 9088d44..59c0b38 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -351,17 +351,17 @@ #ifdef __SIMPLE_DEVICE__ -void update_mei_base_address(void) +static inline void update_mei_base_address(void) { mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); } -bool is_mei_base_address_valid(void) +static inline bool is_mei_base_address_valid(void) { return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } -void me_finalize_smm(void) +static void me_finalize_smm(void) { struct me_hfs hfs; u32 reg32; @@ -396,6 +396,19 @@ RCBA32_OR(FD2, PCH_DISABLE_MEI1); } +void intel_me_finalize_smm(void) +{ + u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + switch (did) { + case 0x1c3a8086: + case 0x1e3a8086: + me_finalize_smm(); + break; + default: + printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); + } +} + #else /* Prepare ME for MEI messages */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib08c0eb4b01e10aa38efac434ff23a488e9e2787 Gerrit-Change-Number: 42051 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: nb/intel/pineview: Guard {MCH,DMI,EP}BAR macros
by Nico Huber (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Damien Zammit, Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49746 ) Change subject: nb/intel/pineview: Guard {MCH,DMI,EP}BAR macros ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49746/comment/f49e1d7e_aa5d0896 PS4, Line 9: should not have : any functional impact how so? -- To view, visit https://review.coreboot.org/c/coreboot/+/49746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8be8d7b8a0f289d2be76d3dec43999f6b42e3265 Gerrit-Change-Number: 49746 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 06 Feb 2021 12:40:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable
by James (Code Review) 06 Feb '21

06 Feb '21

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39074 ) Change subject: sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable ...................................................................... sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable If the Management Engine is in an inoperable mode, e.g. if me_cleaner is used, hide the Management Engine Interface device so the OS doesn't try to access it. Enable the MEI in device trees of Ibex Peak, Cougar Point and Panther Point boards where they have been disabled. Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/ibexpeak/me.c 11 files changed, 18 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39074/1 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index b03e2f9..3c0d278 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -54,7 +54,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 808e057..fb2876f 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -74,7 +74,9 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - device pci 16.0 off end # MEI + device pci 16.0 on # MEI + subsystemid 0x17aa 0x215f + end device pci 16.2 on # IDE/SATA subsystemid 0x17aa 0x2161 end diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 53bd16f..222825b 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -72,7 +72,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index c91b04e..314ca43 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -72,7 +72,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index ee612cd..7483c46 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -75,7 +75,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 2d15d87..510fa9e 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -71,7 +71,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 5ae1427..7e9d9bb 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -71,7 +71,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index bf1c171..97674d8 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -66,7 +66,9 @@ register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x040069" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1025 0x0379 + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R, only management boot device pci 16.3 off end # Management Engine KT diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 15f99cd..280dcb0 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -692,6 +692,8 @@ switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_ERROR_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: intel_me_hide(dev); break; @@ -717,9 +719,7 @@ */ break; - case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f13ced9..88558e3 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -681,6 +681,8 @@ switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_ERROR_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: intel_me_hide(dev); break; @@ -721,9 +723,7 @@ */ break; - case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 63dff6a..aa1c002 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -577,6 +577,8 @@ switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_ERROR_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: intel_me_hide(dev); break; @@ -595,9 +597,7 @@ */ break; - case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e Gerrit-Change-Number: 39074 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
by Arthur Heymans (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49749 ) Change subject: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/northbridge/intel/haswell/haswell.h: https://review.coreboot.org/c/coreboot/+/49749/comment/9d2a2c91_b231ff07 PS4, Line 64: EPBAR64 Is the reason for keeping those here, that older Intel NB don't have any EP/DMI 64bit registers? -- To view, visit https://review.coreboot.org/c/coreboot/+/49749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42 Gerrit-Change-Number: 49749 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 06 Feb 2021 10:57:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/broadwell: Use common {DMI,EP,MCH}BAR accessors
by Arthur Heymans (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50169 ) Change subject: soc/intel/broadwell: Use common {DMI,EP,MCH}BAR accessors ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04dbeade44d480301c9f7d336449bc54e56cb7bc Gerrit-Change-Number: 50169 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 06 Feb 2021 10:54:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors
by Arthur Heymans (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49748 ) Change subject: nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66 Gerrit-Change-Number: 49748 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 06 Feb 2021 10:53:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/ironlake: Avoid pointer arithmetics
by Arthur Heymans (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49747 ) Change subject: nb/intel/ironlake: Avoid pointer arithmetics ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I959e7378a8bf46fd1772192090a751d7a2f6f470 Gerrit-Change-Number: 49747 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 06 Feb 2021 10:51:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/pineview: Guard {MCH,DMI,EP}BAR macros
by Arthur Heymans (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Nico Huber, Damien Zammit, Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49746 ) Change subject: nb/intel/pineview: Guard {MCH,DMI,EP}BAR macros ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8be8d7b8a0f289d2be76d3dec43999f6b42e3265 Gerrit-Change-Number: 49746 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Damien Zammit Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 06 Feb 2021 10:51:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/x4x: Constify write leveling arrays
by Arthur Heymans (Code Review) 06 Feb '21

06 Feb '21

Attention is currently required from: Damien Zammit, Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49403 ) Change subject: nb/intel/x4x: Constify write leveling arrays ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3be3952aaba1fe2da5490b071b4e3609773e84a5 Gerrit-Change-Number: 49403 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Damien Zammit Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 06 Feb 2021 10:48:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021