coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncar
by Felix Held (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50400 ) Change subject: soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncar ...................................................................... soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncar The same functionality is needed on Cezanne. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45 --- M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/picasso/memmap.c 2 files changed, 54 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/50400/1 diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index 9efe959..470b517 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -1,9 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <amdblocks/memmap.h> #include <console/console.h> #include <cbmem.h> -#include <amdblocks/memmap.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/smm.h> +#include <fsp/util.h> +#include <FspGuids.h> +#include <memrange.h> +#include <stdint.h> void memmap_stash_early_dram_usage(void) { @@ -27,3 +32,50 @@ return e; } + +/* + * For data stored in TSEG, ensure TValid is clear so R/W access can reach + * the DRAM when not in SMM. + */ +static void clear_tvalid(void) +{ + msr_t hwcr = rdmsr(HWCR_MSR); + msr_t mask = rdmsr(SMM_MASK_MSR); + int tvalid = !!(mask.lo & SMM_TSEG_VALID); + + if (hwcr.lo & SMM_LOCK) { + if (!tvalid) /* not valid but locked means still accessible */ + return; + + printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); + return; + } + + mask.lo &= ~SMM_TSEG_VALID; + wrmsr(SMM_MASK_MSR, mask); +} + +void smm_region(uintptr_t *start, size_t *size) +{ + static int once; + struct range_entry tseg; + int status; + + *start = 0; + *size = 0; + + status = fsp_find_range_hob(&tseg, AMD_FSP_TSEG_HOB_GUID.b); + + if (status < 0) { + printk(BIOS_ERR, "Error: unable to find TSEG HOB\n"); + return; + } + + *start = (uintptr_t)range_entry_base(&tseg); + *size = range_entry_size(&tseg); + + if (!once) { + clear_tvalid(); + once = 1; + } +} diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 8424d46..970d1373d 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -3,60 +3,11 @@ #include <assert.h> #include <stdint.h> #include <console/console.h> -#include <cpu/x86/smm.h> -#include <cpu/amd/msr.h> #include <arch/bert_storage.h> #include <memrange.h> #include <fsp/util.h> #include <FspGuids.h> -/* - * For data stored in TSEG, ensure TValid is clear so R/W access can reach - * the DRAM when not in SMM. - */ -static void clear_tvalid(void) -{ - msr_t hwcr = rdmsr(HWCR_MSR); - msr_t mask = rdmsr(SMM_MASK_MSR); - int tvalid = !!(mask.lo & SMM_TSEG_VALID); - - if (hwcr.lo & SMM_LOCK) { - if (!tvalid) /* not valid but locked means still accessible */ - return; - - printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); - return; - } - - mask.lo &= ~SMM_TSEG_VALID; - wrmsr(SMM_MASK_MSR, mask); -} - -void smm_region(uintptr_t *start, size_t *size) -{ - static int once; - struct range_entry tseg; - int status; - - *start = 0; - *size = 0; - - status = fsp_find_range_hob(&tseg, AMD_FSP_TSEG_HOB_GUID.b); - - if (status < 0) { - printk(BIOS_ERR, "Error: unable to find TSEG HOB\n"); - return; - } - - *start = (uintptr_t)range_entry_base(&tseg); - *size = range_entry_size(&tseg); - - if (!once) { - clear_tvalid(); - once = 1; - } -} - void bert_reserved_region(void **start, size_t *size) { struct range_entry bert; -- To view, visit https://review.coreboot.org/c/coreboot/+/50400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45 Gerrit-Change-Number: 50400 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__
by Felix Held (Code Review) 08 Feb '21

08 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50399 ) Change subject: soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__ ...................................................................... soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__ No PCI or PNP functions are used in here. TEST=Timeless build results in identical image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812 --- M src/soc/amd/picasso/memmap.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/50399/1 diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 04c2fd8..8424d46 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#define __SIMPLE_DEVICE__ - #include <assert.h> #include <stdint.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812 Gerrit-Change-Number: 50399 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__
by Felix Held (Code Review) 08 Feb '21

08 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50398 ) Change subject: soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__ ...................................................................... soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__ No PCI or PNP functions are used in here. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I46851656db1f1866a82f06ceab67c93019cc6af1 --- M src/soc/amd/stoneyridge/memmap.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/50398/1 diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 67a4319..32790ec 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#define __SIMPLE_DEVICE__ - #include <assert.h> #include <stdint.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46851656db1f1866a82f06ceab67c93019cc6af1 Gerrit-Change-Number: 50398 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: prog_loaders: Remove prog_locate()
by Aaron Durbin (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Furquan Shaikh, Lee Leahy, Julius Werner, Huang Jin, Patrick Rudolph. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49337 ) Change subject: prog_loaders: Remove prog_locate() ...................................................................... Patch Set 7: (1 comment) File src/include/program_loading.h: https://review.coreboot.org/c/coreboot/+/49337/comment/ea45f395_6243970d PS7, Line 134: int prog_locate_hook(struct prog *prog); Does this do anything if prog_locate() is no more? -- To view, visit https://review.coreboot.org/c/coreboot/+/49337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a5525f66e1d5f3a632e8f6f0ed9e116e3cebfcf Gerrit-Change-Number: 49337 Gerrit-PatchSet: 7 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 18:44:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Add cbfs_alloc() primitive and combine cbfs_load() and cbfs_map()
by Aaron Durbin (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Furquan Shaikh, Julius Werner. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49334 ) Change subject: cbfs: Add cbfs_alloc() primitive and combine cbfs_load() and cbfs_map() ...................................................................... Patch Set 7: (1 comment) File src/include/cbfs.h: https://review.coreboot.org/c/coreboot/+/49334/comment/5248525a_cb028c6a PS7, Line 245: ro I believe this should be _cbfs_load(name, buf, size, false, type); -- To view, visit https://review.coreboot.org/c/coreboot/+/49334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fe0645387c0e9053ad5c15744437940fc904392 Gerrit-Change-Number: 49334 Gerrit-PatchSet: 7 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 18:43:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Hook up FSP repository
by Ravishankar Sarawadi (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Felix Singer, Wonkyu Kim, Tim Wawrzynczak, Subrata Banik, Srinidhi N Kaushik, Raj Astekar, Nathaniel L Desimone. Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48713 ) Change subject: soc/intel/tigerlake: Hook up FSP repository ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: Any ETA for merge? https://partnerissuetracker.corp.google.com/issues/175957775 is blocked on this. -- To view, visit https://review.coreboot.org/c/coreboot/+/48713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e694b91be7734dd98665051a6a3d9eccab7dac7 Gerrit-Change-Number: 48713 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 18:13:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
by Furquan Shaikh (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Shreesh Chhabbi, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Raj Astekar, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design ...................................................................... Patch Set 34: (1 comment) Patchset: PS34: > Hi Furquan, I updated the commit message. Removed up3 v/s up4 condition, added note that S0i3. […] Is there a document/addendum that says UP3 and UP4 both cannot achieve S0i2.2/S0i3.3/S0i3.4. The restriction on UP4 as implemented in this code does not match PDG. -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 34 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 18:10:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
by Shreesh Chhabbi (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Shreesh Chhabbi, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Raj Astekar, Patrick Rudolph. Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design ...................................................................... Patch Set 34: (1 comment) Patchset: PS34: Hi Furquan, I updated the commit message. Removed up3 v/s up4 condition, added note that S0i3.1 is deepest state on tgl up3 based platforms and added test result from delbin. -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 34 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 18:07:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
by Shreesh Chhabbi (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi. Shreesh Chhabbi has uploaded a new patch set (#34) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design ...................................................................... soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design This change uses the following information to determine the appropriate S0ix states to enable as per PDG document: 607872 for TGL UP3 UP Rev2p2 (section 10.13): 1. H/W design - external phy gating, external clk gating, external bypass 2. Devices enabled at runtime - CNVi, ISH In some cases, it is recommended to use a shallower state for S0ix even if the higher state can be achieved (e.g. with external gating not enabled). This recommendation is because the shallower state is determined to provide better power savings as per the above document. On tigerlake up3 based platforms, deepest S0ix substate is S0i3.1. BUG=b:177821896 TEST=Build coreboot for volteer. Verify that deepest S0ix substate reached is S0i3.1. Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 59 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/34 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 34 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
by Shreesh Chhabbi (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Shreesh Chhabbi, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Raj Astekar, Patrick Rudolph. Shreesh Chhabbi has uploaded a new patch set (#33) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design ...................................................................... soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design This change uses the following information to determine the appropriate S0ix states to enable as per PDG document: 607872 for TGL UP3 UP Rev2p2 (section 10.13): 1. H/W design - external phy gating, external clk gating, external bypass 2. Devices enabled at runtime - CNVi, ISH In some cases, it is recommended to use a shallower state for S0ix even if the higher state can be achieved (e.g. with external gating not enabled). This recommendation is because the shallower state is determined to provide better power savings as per the above document. BUG=b:177821896 TEST=Build coreboot for volteer. Verify that deepest S0ix substate reached is S0i3.1. Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 59 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 33 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2021