coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/volteer: Enable external bypass, clkgate & phygate
by Furquan Shaikh (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Shreesh Chhabbi, Sukumar Ghorai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50290 ) Change subject: mb/google/volteer: Enable external bypass, clkgate & phygate ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > From Delbin: […] And is S0i3.1 the lowest state expected on Delbin? Can you please capture these observations as part of the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/50290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Gerrit-Change-Number: 50290 Gerrit-PatchSet: 6 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:58:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Enable external bypass, clkgate & phygate
by Sukumar Ghorai (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Shreesh Chhabbi. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50290 ) Change subject: mb/google/volteer: Enable external bypass, clkgate & phygate ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > Can you please capture in the commit message - what is the deepest S0ix state expected and what is o […] From Delbin: localhost ~ # cat /sys/kernel/debug/pmc_core/substate_residencies status substate residency Enabled S0i2.0 0 Enabled S0i2.1 0 S0i2.2 0 Enabled S0i3.0 0 Enabled S0i3.1 337578 S0i3.2 0 S0i3.3 0 S0i3.4 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/50290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Gerrit-Change-Number: 50290 Gerrit-PatchSet: 6 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:56:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
by Sukumar Ghorai (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Shreesh Chhabbi, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Raj Astekar, Patrick Rudolph. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design ...................................................................... Patch Set 32: Code-Review+1 (1 comment) Patchset: PS32: localhost ~ # cat /sys/kernel/debug/pmc_core/substate_residencies status substate residency Enabled S0i2.0 0 Enabled S0i2.1 0 S0i2.2 0 Enabled S0i3.0 0 Enabled S0i3.1 337578 S0i3.2 0 S0i3.3 0 S0i3.4 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 32 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:55:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: Modify touchpad setting for Jelboz
by Martin Roth (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Kane Chen. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49742 ) Change subject: mb/google/zork/var/shuboz: Modify touchpad setting for Jelboz ...................................................................... Patch Set 13: (1 comment) File src/mainboard/google/zork/variants/shuboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/49742/comment/b96361ed_f2ef73e6 PS13, Line 64: ACPI_GPIO_IRQ_EDGE_LOW I think Level is correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/49742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679 Gerrit-Change-Number: 49742 Gerrit-PatchSet: 13 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Randy I-Fan Wang <ifanw(a)google.com> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:51:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
by Sukumar Ghorai (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Shreesh Chhabbi, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Raj Astekar, Patrick Rudolph. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design ...................................................................... Patch Set 32: (1 comment) Patchset: PS32: Verified following two patches and working fine: https://review.coreboot.org/c/coreboot/+/49766 https://review.coreboot.org/c/coreboot/+/50290 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 32 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:49:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/selfboot.c: Remove unnecessary whitespace
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50397 ) Change subject: lib/selfboot.c: Remove unnecessary whitespace ...................................................................... lib/selfboot.c: Remove unnecessary whitespace Change-Id: Ica4254297f5d05e75f852d7e9a9e7bb833dfcea7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/selfboot.c 1 file changed, 54 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/50397/1 diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index c5ad525..a08dcab 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -53,67 +53,66 @@ uint32_t compression, int flags) { - unsigned char *middle, *end; - printk(BIOS_DEBUG, "Loading Segment: addr: %p memsz: 0x%016zx filesz: 0x%016zx\n", - dest, memsz, len); + unsigned char *middle, *end; + printk(BIOS_DEBUG, "Loading Segment: addr: %p memsz: 0x%016zx filesz: 0x%016zx\n", + dest, memsz, len); - /* Compute the boundaries of the segment */ - end = dest + memsz; + /* Compute the boundaries of the segment */ + end = dest + memsz; - /* Copy data from the initial buffer */ - switch (compression) { - case CBFS_COMPRESS_LZMA: { - printk(BIOS_DEBUG, "using LZMA\n"); - timestamp_add_now(TS_START_ULZMA); - len = ulzman(src, len, dest, memsz); - timestamp_add_now(TS_END_ULZMA); - if (!len) /* Decompression Error. */ - return 0; - break; - } - case CBFS_COMPRESS_LZ4: { - printk(BIOS_DEBUG, "using LZ4\n"); - timestamp_add_now(TS_START_ULZ4F); - len = ulz4fn(src, len, dest, memsz); - timestamp_add_now(TS_END_ULZ4F); - if (!len) /* Decompression Error. */ - return 0; - break; - } - case CBFS_COMPRESS_NONE: { - printk(BIOS_DEBUG, "it's not compressed!\n"); - memcpy(dest, src, len); - break; - } - default: - printk(BIOS_INFO, "CBFS: Unknown compression type %d\n", compression); + /* Copy data from the initial buffer */ + switch (compression) { + case CBFS_COMPRESS_LZMA: { + printk(BIOS_DEBUG, "using LZMA\n"); + timestamp_add_now(TS_START_ULZMA); + len = ulzman(src, len, dest, memsz); + timestamp_add_now(TS_END_ULZMA); + if (!len) /* Decompression Error. */ return 0; - } - /* Calculate middle after any changes to len. */ - middle = dest + len; - printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx) <- %08lx\n", - (unsigned long)dest, + break; + } + case CBFS_COMPRESS_LZ4: { + printk(BIOS_DEBUG, "using LZ4\n"); + timestamp_add_now(TS_START_ULZ4F); + len = ulz4fn(src, len, dest, memsz); + timestamp_add_now(TS_END_ULZ4F); + if (!len) /* Decompression Error. */ + return 0; + break; + } + case CBFS_COMPRESS_NONE: { + printk(BIOS_DEBUG, "it's not compressed!\n"); + memcpy(dest, src, len); + break; + } + default: + printk(BIOS_INFO, "CBFS: Unknown compression type %d\n", compression); + return 0; + } + /* Calculate middle after any changes to len. */ + middle = dest + len; + printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx) <- %08lx\n", + (unsigned long)dest, + (unsigned long)middle, + (unsigned long)end, + (unsigned long)src); + + /* Zero the extra bytes between middle & end */ + if (middle < end) { + printk(BIOS_DEBUG, + "Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n", (unsigned long)middle, - (unsigned long)end, - (unsigned long)src); + (unsigned long)(end - middle)); - /* Zero the extra bytes between middle & end */ - if (middle < end) { - printk(BIOS_DEBUG, - "Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n", - (unsigned long)middle, - (unsigned long)(end - middle)); + /* Zero the extra bytes */ + memset(middle, 0, end - middle); + } - /* Zero the extra bytes */ - memset(middle, 0, end - middle); - } - - /* - * Each architecture can perform additional operations - * on the loaded segment - */ - prog_segment_loaded((uintptr_t)dest, memsz, flags); - + /* + * Each architecture can perform additional operations + * on the loaded segment + */ + prog_segment_loaded((uintptr_t)dest, memsz, flags); return 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/50397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica4254297f5d05e75f852d7e9a9e7bb833dfcea7 Gerrit-Change-Number: 50397 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Enable external bypass, clkgate & phygate
by Furquan Shaikh (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Shreesh Chhabbi, Sukumar Ghorai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50290 ) Change subject: mb/google/volteer: Enable external bypass, clkgate & phygate ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > Verified following two patch and working fine. […] Can you please capture in the commit message - what is the deepest S0ix state expected and what is observed? This will be helpful later on to identify any regressions. -- To view, visit https://review.coreboot.org/c/coreboot/+/50290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Gerrit-Change-Number: 50290 Gerrit-PatchSet: 6 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:46:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Correct AT24 NVM address size
by Daniel Kang (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Bingbu Cao, Paul Menzel. Daniel Kang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49633 ) Change subject: mb/google/volteer: Correct AT24 NVM address size ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Can we merge this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/49633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6c3eac1e023b981217e1d7dc06587fc46b1a02 Gerrit-Change-Number: 49633 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Bingbu Cao <bingbu.cao(a)intel.com> Gerrit-Reviewer: Bingbu Cao <bingbu.cao(a)linux.intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Bingbu Cao <bingbu.cao(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:46:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: Adjust touchscreen settings
by Martin Roth (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Kane Chen. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50228 ) Change subject: mb/google/zork/var/shuboz: Adjust touchscreen settings ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50228/comment/1bd86cc8_ef7c5ba5 PS3, Line 12: b:174447201 is this the correct bug number? Is this supposed to be b/174442484? -- To view, visit https://review.coreboot.org/c/coreboot/+/50228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d Gerrit-Change-Number: 50228 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Randy I-Fan Wang <ifanw(a)google.com> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:45:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size
by Benjamin Doron (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Michael Niewöhner. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45002 ) Change subject: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/cannonlake/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/45002/comment/9966a026_acb70b02 PS4, Line 21: > Done `commonlib/helpers.h` is chain-included through `soc/systemagent.h`, `intelblocks/systemagent.h`, `stddef.h`. -- To view, visit https://review.coreboot.org/c/coreboot/+/45002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Gerrit-Change-Number: 45002 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:43:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit February 2021