coreboot-gerrit February 2021

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Change in coreboot[master]: mb/google/volteer: Enable external bypass, clkgate & phygate
by Sukumar Ghorai (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Shreesh Chhabbi. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50290 ) Change subject: mb/google/volteer: Enable external bypass, clkgate & phygate ...................................................................... Patch Set 6: Code-Review+1 (1 comment) Patchset: PS6: Verified following two patch and working fine. https://review.coreboot.org/c/coreboot/+/49766 https://review.coreboot.org/c/coreboot/+/50290 -- To view, visit https://review.coreboot.org/c/coreboot/+/50290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Gerrit-Change-Number: 50290 Gerrit-PatchSet: 6 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:40:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot/bootmode: Add weak fill_lb_gpios
by Aaron Durbin (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Raul Rangel. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50341 ) Change subject: security/vboot/bootmode: Add weak fill_lb_gpios ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ca8f0dba9fd4a868bc7b636e4ed04cbf8dfab0 Gerrit-Change-Number: 50341 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:34:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Move trivial wrappers to static inlines
by Aaron Durbin (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Furquan Shaikh, Julius Werner. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49331 ) Change subject: cbfs: Move trivial wrappers to static inlines ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0170401b2a70c158691b6eb56c7e312553afad1 Gerrit-Change-Number: 49331 Gerrit-PatchSet: 6 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:33:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: memlayout: Store region sizes as separate symbols
by Aaron Durbin (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Philipp Hug, Furquan Shaikh, Marshall Dawson, Julius Werner, ron minnich, Felix Held. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49332 ) Change subject: memlayout: Store region sizes as separate symbols ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Patchset: PS6: The rmodule parsing code may get tripped up by having symbols whose value collide in the expected address space. For those on this CL, please keep that in mind if we see issues after this CL lands. -- To view, visit https://review.coreboot.org/c/coreboot/+/49332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373 Gerrit-Change-Number: 49332 Gerrit-PatchSet: 6 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:32:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/crb: Support CapCRBIdleBypass properly
by build bot (Jenkins) (Code Review) 08 Feb '21

08 Feb '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48329 ) Change subject: drivers/crb: Support CapCRBIdleBypass properly ...................................................................... Patch Set 4: (2 comments) File src/drivers/crb/tpm.c: https://review.coreboot.org/c/coreboot/+/48329/comment/5b930c1c_192dd243 PS4, Line 222: if (!cap_idlebypass && (read8(CRB_REG(cur_loc, CRB_REG_STATUS)) & CRB_REG_STATUS_IDLE) == 0) { line over 96 characters https://review.coreboot.org/c/coreboot/+/48329/comment/403f6023_bfe6667c PS4, Line 223: rc = crb_wait_for_reg32(CRB_REG(cur_loc, CRB_REG_STATUS), 250, CRB_REG_STATUS_IDLE, line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/48329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ae1c34bedeed681a27ceb9a117e3aa11da805b3 Gerrit-Change-Number: 48329 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:07:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size
by Benjamin Doron (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Michael Niewöhner. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45002 ) Change subject: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/cannonlake/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/45002/comment/9346508b_c44aea80 PS4, Line 21: > It compiled locally (HOSTGCC). But I do see that its used. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Gerrit-Change-Number: 45002 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:07:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration
by Benjamin Doron (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50048 ) Change subject: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/50048/comment/adce21fe_527d33ef PS5, Line 332: } > The (implicit) else case would change depending on the defaults in > the FSP binary. Is this change intended? Currently, only asrock/h110m and intel/kblrvp (rvp8) don't define chipset_lockdown. This means that they use CHIPSET_LOCKDOWN_FSP ("0" in the enum). Regardless, I do not intend to change functionality. > If yes, how to test / verify it? > > If we can't, why do we drag get_lockdown_config() around when only > one setting is supported? (IIRC, it was already broken when added.) How broken is it? Later platforms define the else case. It appears to mostly only break assumptions. Based on coreboot logs, SMM is locked before FSP-S, so the only thing this patch might break is nvramtool. And perhaps the fallback mechanism, which is a big(ger) issue. In general, get_lockdown_config() also determines SPI lockdown UPDs. Is this what broke in the past? -- To view, visit https://review.coreboot.org/c/coreboot/+/50048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab97f545597388d9c4811b5baac82d3e06d86484 Gerrit-Change-Number: 50048 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 17:03:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Set Port C VREF as per EEPROM config
by Patrick Rudolph (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Patrick Rudolph, Christian Walter, Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50396 ) Change subject: mb/prodrive/hermes: Set Port C VREF as per EEPROM config ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4 Gerrit-Change-Number: 50396 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 16:50:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Set Port C VREF as per EEPROM config
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50390 ) Change subject: mb/prodrive/hermes: Set Port C VREF as per EEPROM config ...................................................................... Abandoned CB:50396 -- To view, visit https://review.coreboot.org/c/coreboot/+/50390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide7f625fcd62d569630462d7f21a7e0ae8801679 Gerrit-Change-Number: 50390 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/prodrive/hermes: Set Port C VREF as per EEPROM config
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50396 ) Change subject: mb/prodrive/hermes: Set Port C VREF as per EEPROM config ...................................................................... mb/prodrive/hermes: Set Port C VREF as per EEPROM config Configure Port C VREF according to the settings in the EEPROM. Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/hermes/hda_verb.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50396/1 diff --git a/src/mainboard/prodrive/hermes/hda_verb.c b/src/mainboard/prodrive/hermes/hda_verb.c index 473a286..be7dbb4 100644 --- a/src/mainboard/prodrive/hermes/hda_verb.c +++ b/src/mainboard/prodrive/hermes/hda_verb.c @@ -172,6 +172,23 @@ AZALIA_ARRAY_SIZES; +static u32 get_port_c_vref_cfg(uint8_t blue_rear_vref) +{ + switch (blue_rear_vref) { + default: + case 0: + return 0x02040000; + case 1: + return 0x02041000; + case 2: + return 0x02044000; + case 3: + return 0x02045000; + case 4: + return 0x02046000; + } +} + static u32 get_internal_audio_cfg(uint8_t internal_audio_connection) { switch (internal_audio_connection) { @@ -208,6 +225,8 @@ const u32 verbs[] = { AZALIA_PIN_CFG(0, 0x1b, config), + 0x0205000d, + get_port_c_vref_cfg(board_cfg->blue_rear_vref), }; azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); -- To view, visit https://review.coreboot.org/c/coreboot/+/50396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4 Gerrit-Change-Number: 50396 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021