coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

1 participants
7192 discussions

Change in coreboot[master]: soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
by Marshall Dawson (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50288 ) Change subject: soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527 Gerrit-Change-Number: 50288 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:08:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/cezanne: Add root_complex
by build bot (Jenkins) (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Angel Pons, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50339 ) Change subject: soc/amd/cezanne: Add root_complex ...................................................................... Patch Set 2: (5 comments) File src/soc/amd/cezanne/root_complex.c: https://review.coreboot.org/c/coreboot/+/50339/comment/b62e8c8c_ec22d6f1 PS2, Line 35: * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 line over 96 characters https://review.coreboot.org/c/coreboot/+/50339/comment/d593b3a0_cf38b8a4 PS2, Line 38: * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE line over 96 characters https://review.coreboot.org/c/coreboot/+/50339/comment/8e4d1754_44812ca0 PS2, Line 43: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 line over 96 characters https://review.coreboot.org/c/coreboot/+/50339/comment/caf0d43c_74e1a2f2 PS2, Line 45: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE line over 96 characters https://review.coreboot.org/c/coreboot/+/50339/comment/4424f4ea_57b541c6 PS2, Line 48: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/50339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Gerrit-Change-Number: 50339 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:06:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/block: Fix guards for PSP transfer buffer
by Raul Rangel (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Julius Werner, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50403 ) Change subject: soc/amd/common/block: Fix guards for PSP transfer buffer ...................................................................... soc/amd/common/block: Fix guards for PSP transfer buffer The transfer buffer is only required when using VBOOT_STARTS_BEFORE_BOOTBLOCK. The VBOOT workbuffer is only required when VBOOT_STARTS_BEFORE_BOOTBLOCK or VBOOT_STARTS_IN_BOOTBLOCK. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3 --- M src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld 2 files changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/50403/1 diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc index d9bd096..1043118 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#if CONFIG(VBOOT) +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) ALIGN_COUNTER(64) _transfer_buffer = .; REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) +#endif +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) || CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) ALIGN_COUNTER(64) VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) #endif @@ -15,6 +17,6 @@ CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) FMAP_CACHE(., FMAP_SIZE) -#if CONFIG(VBOOT) +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) _etransfer_buffer = .; #endif diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index e1f2765..ff6aebf 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -78,13 +78,13 @@ EARLYRAM_STACK(., CONFIG_EARLYRAM_BSP_STACK_SIZE) REGION(apob, CONFIG_PSP_APOB_DRAM_ADDRESS, 64K, 1) -#if CONFIG(VBOOT) +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE) #endif #include "memlayout_transfer_buffer.inc" -#if CONFIG(VBOOT) +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif _ = ASSERT(BOOTBLOCK_END == ((BOOTBLOCK_END + 0xFFFF) & 0xFFFF0000), "Bootblock end must be 16 bit aligned"); -- To view, visit https://review.coreboot.org/c/coreboot/+/50403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3 Gerrit-Change-Number: 50403 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: security/vboot/bootmode: Add weak fill_lb_gpios
by Raul Rangel (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Angel Pons. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50341 ) Change subject: security/vboot/bootmode: Add weak fill_lb_gpios ...................................................................... Patch Set 2: (1 comment) File src/security/vboot/bootmode.c: https://review.coreboot.org/c/coreboot/+/50341/comment/98988e1e_54af4045 PS1, Line 78: } > I'd remove the `return` statement and leave the function body empty. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ca8f0dba9fd4a868bc7b636e4ed04cbf8dfab0 Gerrit-Change-Number: 50341 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:05:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: security/vboot/bootmode: Add weak fill_lb_gpios
by Raul Rangel (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Angel Pons, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50341 to look at the new patch set (#2). Change subject: security/vboot/bootmode: Add weak fill_lb_gpios ...................................................................... security/vboot/bootmode: Add weak fill_lb_gpios This change allows VBOOT to build when the mainboard hasn't implemented any of the VBOOT functions yet. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I42ca8f0dba9fd4a868bc7b636e4ed04cbf8dfab0 --- M src/security/vboot/bootmode.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/50341/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ca8f0dba9fd4a868bc7b636e4ed04cbf8dfab0 Gerrit-Change-Number: 50341 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/cezanne: Add root_complex
by Raul Rangel (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Angel Pons, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50339 ) Change subject: soc/amd/cezanne: Add root_complex ...................................................................... Patch Set 2: (3 comments) File src/soc/amd/cezanne/root_complex.c: https://review.coreboot.org/c/coreboot/+/50339/comment/cff83acd_7376047f PS1, Line 23: reserved_dram_end > To avoid having so much empty space on the left margin, how about moving this to the right side? I tried it, but it was a little confusing. The left shows region variables, and the right shows Kconfig constants. I think keeping it this way makes it more clear. https://review.coreboot.org/c/coreboot/+/50339/comment/e2f097f1_07f8f2db PS1, Line 88: 1MB > nit: MiB Done https://review.coreboot.org/c/coreboot/+/50339/comment/c5c2740a_232fe93b PS1, Line 97: * > nit: remove this `*` to comply with the coding style This is how clang-format formats it. I changed it to the long style which clang-format also likes. -- To view, visit https://review.coreboot.org/c/coreboot/+/50339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Gerrit-Change-Number: 50339 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:05:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/cezanne: Add root_complex
by Raul Rangel (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Angel Pons, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Patrick Georgi, Martin Roth, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50339 to look at the new patch set (#2). Change subject: soc/amd/cezanne: Add root_complex ...................................................................... soc/amd/cezanne: Add root_complex This is a copy/paste of picasso with a few things removed. With this change we can jump into depthcharge. Allocated resources: PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 21c0000 size cde40000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base 100000000 size 30e340000 align 0 gran 0 limit 0 flags e0004200 index 6 PCI: 00:00.0 resource base 40e340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 7 PCI: 00:00.0 resource base 40f000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base 410000000 size 20000000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base cfffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base ceffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b TEST=Boot majolica and see depthcharge finally loading: Starting depthcharge on MAJOLICA... new_rt5682_codec: chip = 0x1A Looking for NVMe Controller 0x3004cac8 @ 00:01:07 src/drivers/flash/memmapped.c:63 flash_setup(): No MMAP windows for SPI flash! Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e --- M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/root_complex.c 2 files changed, 144 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/50339/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Gerrit-Change-Number: 50339 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/cezanne: Enable early LPC support in bootblock stage
by Raul Rangel (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49929 ) Change subject: soc/amd/cezanne: Enable early LPC support in bootblock stage ...................................................................... Patch Set 10: (3 comments) File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/49929/comment/7ad36335_babad728 PS5, Line 27: select SOC_AMD_COMMON_BLOCK_LPC > move this 2 lines up so it's in alphabetical order Done File src/soc/amd/cezanne/include/soc/acpi.h: https://review.coreboot.org/c/coreboot/+/49929/comment/3d1f7b50_f67d0839 PS5, Line 7: PICASSO > CEZANNE Done File src/soc/amd/cezanne/include/soc/southbridge.h: https://review.coreboot.org/c/coreboot/+/49929/comment/6a6fe40c_f1798a71 PS5, Line 13: PM_SERIRQ_NUM_BITS > Can you define a PM_SERIRQ_NUM_BITS_SHIFT and update all the BITS_X to have a value of 0-15 Keeping for now since it matches picasso. -- To view, visit https://review.coreboot.org/c/coreboot/+/49929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767 Gerrit-Change-Number: 49929 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:05:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/cezanne: Enable early LPC support in bootblock stage
by Raul Rangel (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Zheng Bao, Felix Held. Raul Rangel has uploaded a new patch set (#10) to the change originally created by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/49929 ) Change subject: soc/amd/cezanne: Enable early LPC support in bootblock stage ...................................................................... soc/amd/cezanne: Enable early LPC support in bootblock stage Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/early_fch.c A src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/cezanne/include/soc/southbridge.h 5 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/49929/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/49929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767 Gerrit-Change-Number: 49929 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/zork/var/shuboz: Adjust GPIO settings
by Martin Roth (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Bhanu Prakash Maiya, Kane Chen. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50277 ) Change subject: mb/google/zork/var/shuboz: Adjust GPIO settings ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/zork/variants/shuboz/gpio.c: https://review.coreboot.org/c/coreboot/+/50277/comment/dde86ef8_959f3aee PS2, Line 14: /* RAM ID 2 */ : PAD_GPI(GPIO_86, PULL_NONE), Ram ID 2 should be left high at boot as set in the general dalboz board. -- To view, visit https://review.coreboot.org/c/coreboot/+/50277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b Gerrit-Change-Number: 50277 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:01:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2021