coreboot-gerrit February 2021

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Change in coreboot[master]: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Nico Huber, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49749 ) Change subject: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors ...................................................................... Patch Set 6: (1 comment) File src/northbridge/intel/haswell/haswell.h: https://review.coreboot.org/c/coreboot/+/49749/comment/40b88504_f7c219ae PS6, Line 64: #define EPBAR64(x) (*((volatile u64 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) > This won't compile for 64 bit: […] Right, I'll update this patch to add the casts, and make another patch to add the casts to fixed_bars.h -- To view, visit https://review.coreboot.org/c/coreboot/+/49749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42 Gerrit-Change-Number: 49749 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:51:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Benjamin Doron. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45002 ) Change subject: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Gerrit-Change-Number: 45002 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:49:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
by Nico Huber (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49749 ) Change subject: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/northbridge/intel/haswell/haswell.h: https://review.coreboot.org/c/coreboot/+/49749/comment/51719819_60f3f0ad PS6, Line 64: #define EPBAR64(x) (*((volatile u64 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) This won't compile for 64 bit: > In file included from src/northbridge/intel/haswell/haswell.h:37, > from src/northbridge/intel/haswell/raminit.c:21: > src/northbridge/intel/haswell/raminit.c: In function 'report_memory_config': > src/northbridge/intel/common/fixed_bars.h:14:24: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] > 14 | #define MCHBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) > | ^ > src/northbridge/intel/haswell/raminit.c:77:23: note: in expansion of macro 'MCHBAR32' > 77 | const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); > | ^~~~~~~~ As the EPBAR base fits a 32-bit unsigned integer, it will be represented by one and has to be casted to `uintptr_t` first, to match the pointer width. -- To view, visit https://review.coreboot.org/c/coreboot/+/49749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42 Gerrit-Change-Number: 49749 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:48:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size
by Michael Niewöhner (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Benjamin Doron, Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45002 ) Change subject: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Gerrit-Change-Number: 45002 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:43:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add empty CPU driver
by Felix Held (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Patrick Georgi, Martin Roth, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50404 to look at the new patch set (#2). Change subject: soc/amd/cezanne: add empty CPU driver ...................................................................... soc/amd/cezanne: add empty CPU driver Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I54299cadae4cb562e04a16c3b8e051c9c454db79 --- M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/cpu.c 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/50404/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54299cadae4cb562e04a16c3b8e051c9c454db79 Gerrit-Change-Number: 50404 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: add empty CPU driver
by Raul Rangel (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50404 ) Change subject: soc/amd/cezanne: add empty CPU driver ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54299cadae4cb562e04a16c3b8e051c9c454db79 Gerrit-Change-Number: 50404 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:17:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add empty CPU driver
by Felix Held (Code Review) 08 Feb '21

08 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50404 ) Change subject: soc/amd/cezanne: add empty CPU driver ...................................................................... soc/amd/cezanne: add empty CPU driver Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I54299cadae4cb562e04a16c3b8e051c9c454db79 --- M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/cpu.c 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/50404/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 7f59ef4..9a59d5d 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += uart.c ramstage-y += chip.c +ramstage-y += cpu.c ramstage-y += fch.c ramstage-y += fsp_params.c ramstage-y += gpio.c diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c new file mode 100644 index 0000000..5969efb --- /dev/null +++ b/src/soc/amd/cezanne/cpu.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <soc/cpu.h> + +static void zen_2_3_init(struct device *dev) +{ +} + +static struct device_operations cpu_dev_ops = { + .init = zen_2_3_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, CEZANNE_A0_CPUID}, + { 0, 0 }, +}; + +static const struct cpu_driver zen_2_3 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + -- To view, visit https://review.coreboot.org/c/coreboot/+/50404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54299cadae4cb562e04a16c3b8e051c9c454db79 Gerrit-Change-Number: 50404 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/vboot/bootmode: Add weak fill_lb_gpios
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Raul Rangel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50341 ) Change subject: security/vboot/bootmode: Add weak fill_lb_gpios ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ca8f0dba9fd4a868bc7b636e4ed04cbf8dfab0 Gerrit-Change-Number: 50341 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:12:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add root_complex
by Angel Pons (Code Review) 08 Feb '21

08 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50339 ) Change subject: soc/amd/cezanne: Add root_complex ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Gerrit-Change-Number: 50339 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 08 Feb 2021 20:11:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
by Felix Held (Code Review) 08 Feb '21

08 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50288 ) Change subject: soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA ...................................................................... soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50288 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/include/soc/iomap.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 3d0432b..91f0509 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -78,7 +78,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x13) +#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) /* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */ #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527 Gerrit-Change-Number: 50288 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: merged

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coreboot-gerrit February 2021