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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030"
......................................................................
Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030"
This reverts commit 75f6ab35ffefec72e343175686d7ef45b30b0939.
Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030. This causes an issue where the WP pin is not recognized.
BUG=b:179320024
TEST=WP pin shows up properly in crossystem after reverting this change.
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I0850fd085b5ee70522752633900f69d4d3732321
---
M src/soc/amd/picasso/include/soc/gpio.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/50052/2
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Change subject: Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030"
......................................................................
Patch Set 1: Code-Review+2
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Martin Roth has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/49846 )
Change subject: soc/amd/picasso: Change GPIO _HID to AMDI0030
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/50052
to review the following change.
Change subject: Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030"
......................................................................
Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030"
This reverts commit 75f6ab35ffefec72e343175686d7ef45b30b0939.
Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030. This causes an issue where the WP pin is not recognized.
BUG=b:179320024
TEST=WP pin shows up properly in crossystem after reverting this change.
Change-Id: I0850fd085b5ee70522752633900f69d4d3732321
---
M src/soc/amd/picasso/include/soc/gpio.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/50052/1
diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h
index f76c446..0f4507c 100644
--- a/src/soc/amd/picasso/include/soc/gpio.h
+++ b/src/soc/amd/picasso/include/soc/gpio.h
@@ -3,7 +3,7 @@
#ifndef AMD_PICASSO_GPIO_H
#define AMD_PICASSO_GPIO_H
-#define GPIO_DEVICE_NAME "AMDI0030"
+#define GPIO_DEVICE_NAME "AMD0030"
#define GPIO_DEVICE_DESC "GPIO Controller"
#ifndef __ACPI__
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Change subject: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/50048/comment/5bc95570_30c49a99
PS5, Line 332: }
> > > If we can't, why do we drag get_lockdown_config() around when only […]
IMHO, it's easier to drop support for FSP lockdown.
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Change subject: soc/amd/common/memmap: add comment about types in memmap_early_dram
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/memmap.h:
https://review.coreboot.org/c/coreboot/+/50370/comment/da46bae6_d2702c12
PS2, Line 12: /* fixed size types, so the layout in CBFS won't change for 32 vs. 64 bit stages */
> oh, you're right. […]
Ack
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Change subject: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/50048/comment/749ba848_8ee12a1c
PS5, Line 332: }
> > If we can't, why do we drag get_lockdown_config() around when only
> > one setting is supported? (IIRC, it was already broken when added.)
>
> How broken is it? Later platforms define the else case.
I don't know. I didn't look into it in years. I guess everybody just
runs `chipsec` before releasing anything and fixes things up on local
branches (or maybe master too). What I seem to remember from the review
when the chipset_lockdown distinction was first implemented:
Me: This and that is broken on the CHIPSET_LOCKDOWN_FSP path.
Intel: But we set CHIPSET_LOCKDOWN_COREBOOT for all boards in the tree.
See how much they care about security? I don't remember if things were
fixed or if I just gave up reviewing. It was a mess and I don't know
if CHIPSET_LOCKDOWN_FSP ever made sense / worked properly.
>
> It appears to mostly only break assumptions. Based on coreboot logs, SMM is locked before FSP-S, so the only thing this patch might break is nvramtool. And perhaps the fallback mechanism, which is a big(ger) issue.
It depends on the binary. With the current state of this patch, a
binary that defaults to not locking, and coreboot configured to
CHIPSET_LOCKDOWN_FSP, security can be compromised. Maybe
more than without this patch, I guess one needs to read all
the involved code to tell.
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Change subject: soc/amd,intel: Drop s3_resume parameter on FSP functions
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Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
this patch is about the fsp-s functions, so that would be good to have in the commit message; the fsp-m functions still have that parameter. apart from that the patch looks good to me
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