coreboot-gerrit February 2021

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Change in coreboot[4.11_branch]: intel/stm: Place resource list right below MSEG
by Stefan Reinauer (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Marc Jones, Jay Talbott, Eugene Myers. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50312 ) Change subject: intel/stm: Place resource list right below MSEG ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Ie62e2bdccd2d09084cc39a0f2fe32df236c08cd6 Gerrit-Change-Number: 50312 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Attention: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:37:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: cpu/x86/smm: Add overflow check
by Stefan Reinauer (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Marc Jones, Nico Huber, Jay Talbott. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50311 ) Change subject: cpu/x86/smm: Add overflow check ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I28e10d8836ab80c6fec9d3414c795c5e6ff312e8 Gerrit-Change-Number: 50311 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:37:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
by Furquan Shaikh (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Shreesh Chhabbi, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Sukumar Ghorai, Raj Astekar, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design ...................................................................... Patch Set 38: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49766/comment/381233ab_72ed1f03 PS38, Line 21: Deepest state expected on tigerlake up3 based : platforms is S0i3.1. This is not correct. It is S0i3.2 https://review.coreboot.org/c/coreboot/+/49766/comment/358899f0_22cecbe8 PS38, Line 26: S0i3.1 Volteer can reach S0i3.1 only because it uses CNVi. -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 38 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:37:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: cpu/x86/smm: Add smm_size to relocatable smmstub
by Stefan Reinauer (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Marc Jones, Jay Talbott, Arthur Heymans. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50310 ) Change subject: cpu/x86/smm: Add smm_size to relocatable smmstub ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I4948639a513b196382eb38616fe872b72bb7e59e Gerrit-Change-Number: 50310 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:37:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: security/intel/stm: Check for processor STM support
by Stefan Reinauer (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Marc Jones, Jay Talbott. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50309 ) Change subject: security/intel/stm: Check for processor STM support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I312570ca28329490006283251f69dd83ef64af40 Gerrit-Change-Number: 50309 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:37:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: security/intel/stm: Add STM support
by Stefan Reinauer (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Marc Jones, Martin Roth, Jay Talbott. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50308 ) Change subject: security/intel/stm: Add STM support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Ic0131fcada9f43c9817c8a0a942d0419c7023130 Gerrit-Change-Number: 50308 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:37:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: superio/aspeed: setup early serial for AST2600
by Jonathan Zhang (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Subrata Banik. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50374 ) Change subject: superio/aspeed: setup early serial for AST2600 ...................................................................... Patch Set 1: (1 comment) This change is ready for review. File src/superio/aspeed/common/aspeed.h: https://review.coreboot.org/c/coreboot/+/50374/comment/6276f766_b2a9c564 PS1, Line 8: #include "../ast2400/ast2400.h" > do we need this ? Yes, we need to include this header file, so that the code can use definitions such as AST2600_CHIP_ID_REG. -- To view, visit https://review.coreboot.org/c/coreboot/+/50374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib21b054bea2e64e00521807e8aa13e536f643974 Gerrit-Change-Number: 50374 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:32:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Second pass GPIO configuration
by Mathew King (Code Review) 09 Feb '21

09 Feb '21

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50450 ) Change subject: mb/google/guybrush: Second pass GPIO configuration ...................................................................... mb/google/guybrush: Second pass GPIO configuration Configure the non native function GPIOs based on the guybrush reference schematic. BUG=b:177909472 TEST=builds Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 78 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/50450/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index b7d66a3..d3bc7ce 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -13,98 +13,98 @@ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), /* WAKE_L */ PAD_NF(GPIO_2, WAKE_L, PULL_NONE), - /* AGPIO3 */ - PAD_NC(GPIO_3), - /* AGPIO4 */ - PAD_NC(GPIO_4), - /* AGPIO5 */ - PAD_NC(GPIO_5), - /* AGPIO6 */ - PAD_NC(GPIO_6), - /* AGPIO7 */ - PAD_NC(GPIO_7), - /* AGPIO8 */ - PAD_NC(GPIO_8), - /* AGPIO9 */ - PAD_NC(GPIO_9), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* SOC_PEN_DETECT_ODL */ + PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), + /* EN_PP5000_PEN */ + PAD_GPO(GPIO_5, LOW), + /* EN_PP3300_WLAN */ + PAD_GPO(GPIO_6, LOW), + /* EN_PP3300_TCHPAD */ + PAD_GPO(GPIO_7, LOW), + /* EN_PWR_WWAN_X */ + PAD_GPO(GPIO_8, LOW), + /* SOC_TCHPAD_INT_ODL */ + PAD_INT(GPIO_9, PULL_NONE, EDGE_HIGH, STATUS_DELIVERY), /* S0A3 */ PAD_NF(GPIO_10, S0A3, PULL_NONE), - /* AGPIO11 */ - PAD_NC(GPIO_11), - /* AGPIO12 */ - PAD_NC(GPIO_12), + /* SOC_FP_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* SLP_S3_GATED */ + PAD_GPO(GPIO_12, LOW), /* GPIO_13 - GPIO_15: Not available */ /* USB_OC0_L */ PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), - /* AGPIO17 */ - PAD_NC(GPIO_17), - /* AGPIO18 */ - PAD_NC(GPIO_18), + /* SOC_SAR_INT_L */ + PAD_INT(GPIO_17, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* WWAN_AUX_RST_L */ + PAD_GPO(GPIO_18, LOW), /* I2C3_SCL */ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA */ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* AGPIO21 */ - PAD_NC(GPIO_21), - /* AGPIO22 */ - PAD_NC(GPIO_22), + /* SOC_FP_INT_L */ + PAD_INT(GPIO_21, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* EC_SOC_WAKE_L */ + PAD_WAKE(GPIO_22, PULL_NONE, EDGE_LOW, S0i3), /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), - /* AGPIO24 */ - PAD_NC(GPIO_24), + /* WWAN_RST_LWWAN_RST_L */ + PAD_GPO(GPIO_24, LOW), /* GPIO_25: Not available */ /* PCIE_RST0_L */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* PCIE_RST1_L */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* GPIO_28: Not available */ - /* AGPIO29 */ - PAD_NC(GPIO_29), + /* FP_CS_L */ + PAD_GPO(GPIO_29, HIGH), /* ESPI_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* SPI_CS3_L */ PAD_NF(GPIO_31, SPI_CS3_L, PULL_NONE), - /* AGPIO32 */ - PAD_NC(GPIO_32), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), /* GPIO_33 - GPIO_39: Not available */ - /* AGPIO40 */ - PAD_NC(GPIO_40), + /* SSD_AUX_RST_L */ + PAD_GPO(GPIO_40, LOW), /* GPIO_41: Not available */ - /* EGPIO42 */ - PAD_NC(GPIO_42), + /* WWAN_DPR_SAR_ODL */ + PAD_GPO(GPIO_42, LOW), /* GPIO_43 - GPIO_66: Not available */ - /* EGPIO67 */ - PAD_NC(GPIO_67), - /* AGPIO68 */ - PAD_NC(GPIO_68), - /* AGPIO69 */ - PAD_NC(GPIO_69), - /* EGPIO70 */ - PAD_NC(GPIO_70), + /* SOC_BIOS_WP_L */ + PAD_GPI(GPIO_67, PULL_NONE), + /* EN_PP3300_TCHSCR */ + PAD_GPO(GPIO_68, LOW), + /* EN_SPKR */ + PAD_GPO(GPIO_69, LOW), + /* SD_AUX_RST_L */ + PAD_GPO(GPIO_70, LOW), /* GPIO_71 - GPIO_73: Not available */ - /* EGPIO74 */ - PAD_NC(GPIO_74), - /* EGPIO75 */ - PAD_NC(GPIO_75), - /* EGPIO76 */ - PAD_NC(GPIO_76), + /* RAM_ID_CHAN_SEL */ + PAD_GPI(GPIO_74, PULL_NONE), + /* RAM_ID_2 / DEV_BEEP_LRCLK */ + PAD_GPI(GPIO_75, PULL_NONE), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), /* GPIO_77 - GPIO_83: Not available */ - /* AGPIO84 */ - PAD_NC(GPIO_84), - /* AGPIO85 */ - PAD_NC(GPIO_85), + /* EC_SOC_INT_ODL */ + PAD_GPI(GPIO_84, PULL_NONE), + /* WWAN_DISABLE */ + PAD_GPO(GPIO_85, HIGH), /* SPI_CLK2 */ PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), - /* AGPIO87 */ - PAD_NC(GPIO_87), - /* AGPIO88 */ - PAD_NC(GPIO_88), - /* AGPIO89 */ - PAD_NC(GPIO_89), - /* AGPIO90 */ - PAD_NC(GPIO_90), - /* AGPIO91 */ - PAD_NC(GPIO_91), + /* RAM_ID_1 / DEV_BEEP_DATA */ + PAD_GPI(GPIO_87, PULL_NONE), + /* RAM_ID_3 / DEV_BEEP_BCLK */ + PAD_GPI(GPIO_88, PULL_NONE), + /* TCHSCR_INT_ODL */ + PAD_GPI(GPIO_89, PULL_NONE), + /* HP_INT_ODL */ + PAD_GPI(GPIO_90, PULL_NONE), + /* SD_EX_PRSNT_L */ + PAD_GPI(GPIO_91, PULL_NONE), /* CLK_REQ0_L */ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), /* GPIO_93 - GPIO_103: Not available */ @@ -118,8 +118,8 @@ PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* ESPI_ALERT_L */ PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), - /* EGPIO109 */ - PAD_NC(GPIO_109), + /* RAM_ID_0 / DEV_BEEP_EN */ + PAD_GPI(GPIO_109, PULL_NONE), /* GPIO_110 - GPIO_112: Not available */ /* I2C2_SCL */ PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), @@ -130,19 +130,19 @@ /* CLK_REQ2_L */ PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), /* GPIO_117 - GPIO_119: Not available */ - /* EGPIO120 */ - PAD_NC(GPIO_120), - /* EGPIO121 */ - PAD_NC(GPIO_121), + /* TCHSCR_REPORT_EN */ + PAD_GPO(GPIO_120, LOW), + /* TCHSCR_RESET */ + PAD_GPO(GPIO_121, LOW), /* GPIO_122 - GPIO_128: Not available */ - /* AGPIO129 */ - PAD_NC(GPIO_129), - /* AGPIO130 */ - PAD_NC(GPIO_130), + /* SOC_DISABLE_DISP_BL */ + PAD_GPO(GPIO_129, LOW), + /* WLAN_DISABLE */ + PAD_GPO(GPIO_130, HIGH), /* CLK_REQ3_L */ PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), - /* EGPIO132 */ - PAD_NC(GPIO_132), + /* BT_DISABLE */ + PAD_GPO(GPIO_132, HIGH), /* UART1_TXD */ PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), /* UART0_RXD */ @@ -151,8 +151,8 @@ PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), /* UART0_TXD */ PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), - /* AGPIO144 */ - PAD_NC(GPIO_144), + /* FPMCU_BOOT_0 */ + PAD_GPO(GPIO_144, LOW), /* I2C0_SCL */ PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), /* I2C0_SDA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602 Gerrit-Change-Number: 50450 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/cpu: move get_cpu_count to common code
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50406 ) Change subject: soc/amd/picasso/cpu: move get_cpu_count to common code ...................................................................... soc/amd/picasso/cpu: move get_cpu_count to common code Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0690787f492d764a20a4219822eb10fb5cd86de0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50406 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/cpu/noncar/Makefile.inc A src/soc/amd/common/block/cpu/noncar/cpu.c M src/soc/amd/common/block/include/amdblocks/cpu.h M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/include/soc/cpu.h 7 files changed, 14 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc index dd95941..808679d 100644 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += pre_c.S bootblock-y += write_resume_eip.c romstage-y += memmap.c +ramstage-y += cpu.c ramstage-y += memmap.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c new file mode 100644 index 0000000..7c1daf9 --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/cpu.h> +#include <cpu/cpu.h> + +int get_cpu_count(void) +{ + return 1 + (cpuid_ecx(0x80000008) & 0xff); +} diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index 0a93643..50300d5 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -3,6 +3,7 @@ #ifndef AMD_BLOCK_CPU_H #define AMD_BLOCK_CPU_H +int get_cpu_count(void); void write_resume_eip(void); #endif /* AMD_BLOCK_CPU_H */ diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index eba9dfe..2f08dce 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -19,9 +19,9 @@ #include <device/pci.h> #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> +#include <amdblocks/cpu.h> #include <soc/acpi.h> #include <soc/pci_devs.h> -#include <soc/cpu.h> #include <soc/msr.h> #include <soc/southbridge.h> #include <soc/nvs.h> diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 6020ec0..119dd55 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -12,7 +12,7 @@ #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <soc/cpu.h> +#include <amdblocks/cpu.h> #include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <stdlib.h> diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 5979fc6..b18a3b4 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/cpu.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> @@ -41,11 +42,6 @@ x86_mtrr_check(); } -int get_cpu_count(void) -{ - return 1 + (cpuid_ecx(0x80000008) & 0xff); -} - static void set_cstate_io_addr(void) { msr_t cst_addr; diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 3f6cd24..79d5cc6 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -3,7 +3,6 @@ #ifndef AMD_PICASSO_CPU_H #define AMD_PICASSO_CPU_H -int get_cpu_count(void); void check_mca(void); #define RAVEN1_B0_CPUID 0x00810f10 -- To view, visit https://review.coreboot.org/c/coreboot/+/50406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0690787f492d764a20a4219822eb10fb5cd86de0 Gerrit-Change-Number: 50406 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Michael Niewöhner (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Benjamin Doron. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49140/comment/2a6dd9ef_cc218195 PS5, Line 9: maybe add "It is required to make the kernel load `intel_pmc_core`."? https://review.coreboot.org/c/coreboot/+/49140/comment/68a7f65e_e2d4e498 PS5, Line 13: predictably. ... via debugfs. -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:31:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2021