coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/cezanne: Add root_complex
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50339 ) Change subject: soc/amd/cezanne: Add root_complex ...................................................................... soc/amd/cezanne: Add root_complex This is a copy/paste of picasso with a few things removed. With this change we can jump into depthcharge. Allocated resources: PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 21c0000 size cde40000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base 100000000 size 30e340000 align 0 gran 0 limit 0 flags e0004200 index 6 PCI: 00:00.0 resource base 40e340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 7 PCI: 00:00.0 resource base 40f000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base 410000000 size 20000000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base cfffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base ceffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b TEST=Boot majolica and see depthcharge finally loading: Starting depthcharge on MAJOLICA... new_rt5682_codec: chip = 0x1A Looking for NVMe Controller 0x3004cac8 @ 00:01:07 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50339 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/root_complex.c 2 files changed, 144 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Marshall Dawson: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 9a59d5d..ce9f66c 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -31,6 +31,7 @@ ramstage-y += gpio.c ramstage-y += pcie_gpp.c ramstage-y += reset.c +ramstage-y += root_complex.c ramstage-y += uart.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c new file mode 100644 index 0000000..fbbf86b --- /dev/null +++ b/src/soc/amd/cezanne/root_complex.c @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/memmap.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <fsp/util.h> +#include <stdint.h> + +/* + * + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (86KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (64KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +static void read_resources(struct device *dev) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + unsigned int idx = 0; + const struct hob_header *hob = fsp_get_hob_list(); + const struct hob_resource *res; + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_resource(dev, idx++, 0, 0xa0000 / KiB); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_resource(dev, idx++, (1 * MiB) / KiB, + (early_reserved_dram_start - (1 * MiB)) / KiB); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB, + (early_reserved_dram_end - early_reserved_dram_start) / KiB); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_resource(dev, idx++, early_reserved_dram_end / KiB, + (mem_usable - early_reserved_dram_end) / KiB); + + mmconf_resource(dev, MMIO_CONF_BASE); + + if (!hob) { + printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + __func__); + return; + } + + for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { + + if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) + continue; + + res = fsp_hob_header_to_resource(hob); + + if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable) + continue; /* 0 through low usable was set above */ + if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO) + continue; /* Done separately */ + + if (res->type == EFI_RESOURCE_SYSTEM_MEMORY) + ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); + else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) + reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); + else + printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + res->type); + } +} + +static struct device_operations root_complex_operations = { + .read_resources = read_resources, + .set_resources = noop_set_resources, + .enable_resources = pci_dev_enable_resources, +}; + +static const struct pci_driver family17_root_complex __pci_driver = { + .ops = &root_complex_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/50339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Gerrit-Change-Number: 50339 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Add root_complex
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50339 ) Change subject: soc/amd/cezanne: Add root_complex ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50339/comment/b4678910_21c72446 PS2, Line 31: src/drivers/flash/memmapped.c:63 flash_setup(): No MMAP windows for SPI flash! > this problem is fixed Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Gerrit-Change-Number: 50339 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:29:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add root_complex
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth. Felix Held has uploaded a new patch set (#3) to the change originally created by Raul Rangel. ( https://review.coreboot.org/c/coreboot/+/50339 ) Change subject: soc/amd/cezanne: Add root_complex ...................................................................... soc/amd/cezanne: Add root_complex This is a copy/paste of picasso with a few things removed. With this change we can jump into depthcharge. Allocated resources: PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 21c0000 size cde40000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base 100000000 size 30e340000 align 0 gran 0 limit 0 flags e0004200 index 6 PCI: 00:00.0 resource base 40e340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 7 PCI: 00:00.0 resource base 40f000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base 410000000 size 20000000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base cfffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base ceffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b TEST=Boot majolica and see depthcharge finally loading: Starting depthcharge on MAJOLICA... new_rt5682_codec: chip = 0x1A Looking for NVMe Controller 0x3004cac8 @ 00:01:07 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e --- M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/root_complex.c 2 files changed, 144 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/50339/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Gerrit-Change-Number: 50339 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Add root_complex
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50339 ) Change subject: soc/amd/cezanne: Add root_complex ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/root_complex.c: https://review.coreboot.org/c/coreboot/+/50339/comment/a37e8d1c_db97091c PS2, Line 130: } > i only tend to add todos if it's quite non-obvious that something's missing or wrong. […] yeah, let's get this merged and just add the remaining bits later; it nothing too unobvious, so i'm ok with the current state -- To view, visit https://review.coreboot.org/c/coreboot/+/50339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Gerrit-Change-Number: 50339 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:28:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Michael Niewöhner (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Benjamin Doron. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49140/comment/ffa8fdcc_d5c7ae00 PS3, Line 11: > > > > Not needed. SlpS0 is not asserted externally but by the SoC. > > > > > > And the pad doesn't need to be `_NF`? > > > > It can be but it simply doesn't matter because your board doesn't use it. > > > > > > > > > So, the problem seems to be that Linux doesn't differentiate PC10-only and PC10+SlpS0 systems. Iow. there's a check missing here ... https://github.com/torvalds/linux/blob/master/drivers/platform/x86/intel_pm… > > > > > > Well, ideally the system would make it to SlpS0. I think it's correct to warn that this didn't happen. However, if the table doesn't advertise support, it can be argued that the kernel doesn't need to check the default address... > > > > That's the point. When SlpS0 is not advertised there is no need to check/warn for S0Slp. > > > > > > > > To me, this appears deliberate, but I couldn't be sure. > > > > > > > Hmm, somewhere above you wrote Linux prints an error for PC10 on vendor firmware. Did you really mean PC10 or SlpS0? > > > > > > I meant PC10. > > > > > > Are ASPM and L1 substates involved? The vendor firmware has the "ASPM not supported" bit set in FADT and disables L1 substates. > > > > Yes, both are required to get to PC10. > > Ah. That would explain the issues. > > > > In coreboot, I had disabled L1 substates and set ASPM to "L1" on the WLAN's root port to mitigate AER errors. I noticed now that the LAN's root port has disabled ASPM but I'm not sure why (the bit is read-write-once, I'll look into that). > > > > Check Kconfig and devicetree for L1 states. > > The kernel r8169 module always disables ASPM on these Realtek LAN devices because it apparently causes some to stop working or hang the system. The only difference is that coreboot gives ASPM control to the OS, but the vendor firmware does not. Besides that, the module must change ASPM state before accessing some registers. So, perhaps S0ix will not work on this board. Hmmm... just curious, what kernel version exactly? There was some fix recently that should be in mainline or maybe even stable. > So, perhaps S0ix will not work on this board. PC10 worked, so S0ix works. It's just SlpS0 that doesn't work :-) Since it wouldn't have any effect on that board, that's ok. > > Thanks for the help. Can we get this in now? -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:27:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica: Add chromeos support
by Marshall Dawson (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50343 ) Change subject: mb/amd/majolica: Add chromeos support ...................................................................... Patch Set 2: (1 comment) File src/mainboard/amd/majolica/Kconfig: https://review.coreboot.org/c/coreboot/+/50343/comment/9366bc44_d9e24f9f PS2, Line 48: > So I built this with CrOS depthcharge. […] Oh that makes sense, then. It's been a while since I've used it, but yeah it works(worked) and you can try it with a zork platform. Go to Chipset / ChromeOS / Select the "Build for" option. Now, when you go to the Payload menu, you have a DC option. -- To view, visit https://review.coreboot.org/c/coreboot/+/50343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1 Gerrit-Change-Number: 50343 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:22:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex number
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50405 ) Change subject: soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex number ...................................................................... soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex number Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id9042def0f5e9d2fa994d6729c592c7e2152976b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50405 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/cpu.c 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index c898ff7..9992fc5 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -16,6 +16,7 @@ #include <soc/smi.h> #include <soc/iomap.h> #include <console/console.h> +#include <amdblocks/psp.h> /* * MP and SMM loading initialization. @@ -121,10 +122,10 @@ uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - psp_msr = rdmsr(0xc00110a2); + psp_msr = rdmsr(MSR_PSP_ADDR); if (psp_msr.lo == 0) { psp_msr.lo = psp_bar; - wrmsr(0xc00110a2, psp_msr); + wrmsr(MSR_PSP_ADDR, psp_msr); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/50405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9042def0f5e9d2fa994d6729c592c7e2152976b Gerrit-Change-Number: 50405 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Benjamin Doron (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Michael Niewöhner. Hello build bot (Jenkins), Angel Pons, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49140 to look at the new patch set (#5). Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... soc/intel/skylake/acpi: Add PEP table PEP table is applicable to Skylake platform as well. Skylake boards can also use S0ix hooks. Tested on an out-of-tree Acer Aspire VN7-572G (Skylake-U), intel_pmc_core kernel module is loaded and reports statuses predictably. Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi/pch.asl 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/49140/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Benjamin Doron (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Michael Niewöhner. Hello build bot (Jenkins), Angel Pons, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49140 to look at the new patch set (#4). Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... soc/intel/skylake/acpi: Add PEP table PEP table is applicable to Skylake platform as well. Skylake boards can also use S0ix hooks. Tested on an out-of-tree Acer Aspire VN7-572G (Skylake-U), intel_pmc_core kernel module and reports statuses predictably. Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi/pch.asl 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/49140/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Add root_complex
by Marshall Dawson (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50339 ) Change subject: soc/amd/cezanne: Add root_complex ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Gerrit-Change-Number: 50339 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:13:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021