coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/common/psp_gen2: print error for uninitialized MSR_PSP_ADDR
by Raul Rangel (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50448 ) Change subject: soc/amd/common/psp_gen2: print error for uninitialized MSR_PSP_ADDR ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b6362a9eb2344293dad22357651f646774af789 Gerrit-Change-Number: 50448 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Feb 2021 20:46:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: factor out soc_get_psp_base_address
by Raul Rangel (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50447 ) Change subject: soc/amd/common/block/psp: factor out soc_get_psp_base_address ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/soc/amd/common/block/psp/psp_gen2.c: https://review.coreboot.org/c/coreboot/+/50447/comment/17b8b939_f6c25e72 PS2, Line 16: psp_mmio Should we just die instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/50447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989 Gerrit-Change-Number: 50447 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Feb 2021 20:46:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google: order matters in mem_parts_used.txt
by Paul Fagerburg (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Rob Barnes. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50449 ) Change subject: mb/google: order matters in mem_parts_used.txt ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > nit: we could also update the header in existing mem_parts_used.txt files. I updated the ones for dedede and volteer. All of the zork variants use an explicit ID to override the order that the parts are listed in, so the comment wouldn't make sense there. -- To view, visit https://review.coreboot.org/c/coreboot/+/50449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02 Gerrit-Change-Number: 50449 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 20:46:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google: order matters in mem_parts_used.txt
by Paul Fagerburg (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Paul Fagerburg. Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Rob Barnes, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50449 to look at the new patch set (#2). Change subject: mb/google: order matters in mem_parts_used.txt ...................................................................... mb/google: order matters in mem_parts_used.txt * Add comments to mem_parts_used.txt to point out that the order of the entries matters when assigning IDs, so always add a new part to the end of the file. * Update existing mem_parts_used.txt to add the same comment. * No updates to Zork variants, because they use an optional ID, so the order actually doesn't matter there. BUG=b:175898902 TEST=create a new variant of dalboz, trembyle, volteer, waddledee, or waddledoo, and observe that mem_parts_used.txt has the new verbiage. Signed-off-by: Paul Fagerburg <pfagerburg(a)google.com> Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02 --- M src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/kracko/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt M src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt M src/mainboard/google/volteer/variants/copano/memory/mem_parts_used.txt M src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt M util/mainboard/google/dalboz/template/spd/mem_parts_used.txt M util/mainboard/google/trembyle/template/spd/mem_parts_used.txt M util/mainboard/google/volteer/template/memory/mem_parts_used.txt M util/mainboard/google/waddledee/template/memory/mem_parts_used.txt M util/mainboard/google/waddledoo/template/memory/mem_parts_used.txt 14 files changed, 124 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/50449/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02 Gerrit-Change-Number: 50449 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/vboot/bootmode: Add weak fill_lb_gpios
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50341 ) Change subject: security/vboot/bootmode: Add weak fill_lb_gpios ...................................................................... security/vboot/bootmode: Add weak fill_lb_gpios This change allows VBOOT to build when the mainboard hasn't implemented any of the VBOOT functions yet. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I42ca8f0dba9fd4a868bc7b636e4ed04cbf8dfab0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50341 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/vboot/bootmode.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 4f491db..6c05109 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -72,4 +72,8 @@ return 0; } +void __weak fill_lb_gpios(struct lb_gpios *gpios) +{ +} + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/50341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ca8f0dba9fd4a868bc7b636e4ed04cbf8dfab0 Gerrit-Change-Number: 50341 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Enable early LPC support in bootblock stage
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49929 ) Change subject: soc/amd/cezanne: Enable early LPC support in bootblock stage ...................................................................... soc/amd/cezanne: Enable early LPC support in bootblock stage Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49929 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/early_fch.c A src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/cezanne/include/soc/southbridge.h 5 files changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 611260d..a881ef8 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -24,6 +24,7 @@ select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 37ba4c7..8353cb1 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> +#include <amdblocks/lpc.h> #include <amdblocks/smbus.h> #include <console/console.h> #include <soc/southbridge.h> @@ -9,6 +10,8 @@ /* Before console init */ void fch_pre_init(void) { + lpc_early_init(); + enable_acpimmio_decode_pm04(); fch_smbus_init(); fch_enable_cf9_io(); diff --git a/src/soc/amd/cezanne/include/soc/acpi.h b/src/soc/amd/cezanne/include/soc/acpi.h new file mode 100644 index 0000000..6927d93 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/acpi.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMD_CEZANNE_ACPI_H +#define AMD_CEZANNE_ACPI_H + + +#endif /* AMD_CEZANNE_ACPI_H */ diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index b91ff27..73640f5 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -4,6 +4,7 @@ #define AMD_CEZANNE_IOMAP_H /* MMIO Ranges */ +#define SPI_BASE_ADDRESS 0xfec10000 /* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000 diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 8623063..9353e13 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -8,6 +8,17 @@ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PWR_RESET_CFG 0x10 #define TOGGLE_ALL_PWR_GOOD (1 << 1) +#define PM_SERIRQ_CONF 0x54 +#define PM_SERIRQ_NUM_BITS_17 0x0000 +#define PM_SERIRQ_NUM_BITS_18 0x0004 +#define PM_SERIRQ_NUM_BITS_19 0x0008 +#define PM_SERIRQ_NUM_BITS_20 0x000c +#define PM_SERIRQ_NUM_BITS_21 0x0010 +#define PM_SERIRQ_NUM_BITS_22 0x0014 +#define PM_SERIRQ_NUM_BITS_23 0x0018 +#define PM_SERIRQ_NUM_BITS_24 0x001c +#define PM_SERIRQ_MODE BIT(6) +#define PM_SERIRQ_ENABLE BIT(7) #define PM_EVT_BLK 0x60 #define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ #define PCIEXPWAK_STS BIT(14) @@ -39,6 +50,10 @@ #define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_RTC_WAKE_EN BIT(29) +#define PM_LPC_GATING 0xec +#define PM_LPC_AB_NO_BYPASS_EN BIT(2) +#define PM_LPC_A20_EN BIT(1) +#define PM_LPC_ENABLE BIT(0) #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767 Gerrit-Change-Number: 49929 Gerrit-PatchSet: 11 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: templates: mem_parts_used.txt say that order matters
by Rob Barnes (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Paul Fagerburg. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50449 ) Change subject: templates: mem_parts_used.txt say that order matters ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: nit: we could also update the header in existing mem_parts_used.txt files. -- To view, visit https://review.coreboot.org/c/coreboot/+/50449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02 Gerrit-Change-Number: 50449 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 20:36:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: factor out soc_get_psp_base_address
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50447 ) Change subject: soc/amd/common/block/psp: factor out soc_get_psp_base_address ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/psp/psp_gen2.c: https://review.coreboot.org/c/coreboot/+/50447/comment/fd132bc3_97adb112 PS1, Line 20: 0 > it's both wrong, but it should return 0. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989 Gerrit-Change-Number: 50447 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 20:36:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: factor out soc_get_psp_base_address
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50447 to look at the new patch set (#2). Change subject: soc/amd/common/block/psp: factor out soc_get_psp_base_address ...................................................................... soc/amd/common/block/psp: factor out soc_get_psp_base_address Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989 --- M src/soc/amd/common/block/psp/psp_gen2.c 1 file changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/50447/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989 Gerrit-Change-Number: 50447 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
by Sukumar Ghorai (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Furquan Shaikh, Shreesh Chhabbi, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Raj Astekar, Patrick Rudolph. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design ...................................................................... Patch Set 37: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49766/comment/cb0a9b89_36290484 PS37, Line 77: S0i3.2 > Hi Sukumar, can you please let us know? @Shreesh, my mistake. S0i3.2 will get disable as part of CNVi check only. -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 37 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 20:31:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2021