coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/common/block/psp: factor out soc_get_psp_base_address
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50447 ) Change subject: soc/amd/common/block/psp: factor out soc_get_psp_base_address ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/psp/psp_gen2.c: https://review.coreboot.org/c/coreboot/+/50447/comment/73079d7a_07c6667d PS1, Line 20: 0 > This would previously return 0. Now it will return 0 + PSP_MAILBOX_OFFSET. Not sure we want that... it's both wrong, but it should return 0. i'll push an update later -- To view, visit https://review.coreboot.org/c/coreboot/+/50447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989 Gerrit-Change-Number: 50447 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 20:04:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/blocks/lpc: Remove common SPI registers
by Raul Rangel (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50446 to look at the new patch set (#3). Change subject: soc/amd/common/blocks/lpc: Remove common SPI registers ...................................................................... soc/amd/common/blocks/lpc: Remove common SPI registers Use the SoC versions instead. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0 --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/common/block/lpc/lpc_util.c M src/soc/amd/common/block/spi/fch_spi.c M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 5 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/50446/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0 Gerrit-Change-Number: 50446 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/psp: factor out soc_get_psp_base_address
by Raul Rangel (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50447 ) Change subject: soc/amd/common/block/psp: factor out soc_get_psp_base_address ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/psp/psp_gen2.c: https://review.coreboot.org/c/coreboot/+/50447/comment/b6edf816_6b5b8624 PS1, Line 20: 0 This would previously return 0. Now it will return 0 + PSP_MAILBOX_OFFSET. Not sure we want that... -- To view, visit https://review.coreboot.org/c/coreboot/+/50447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989 Gerrit-Change-Number: 50447 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Feb 2021 19:38:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncar
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50400 ) Change subject: soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncar ...................................................................... soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncar The same functionality is needed on Cezanne. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50400 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/picasso/memmap.c 2 files changed, 54 insertions(+), 51 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index 9efe959..470b517 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -1,9 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <amdblocks/memmap.h> #include <console/console.h> #include <cbmem.h> -#include <amdblocks/memmap.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/smm.h> +#include <fsp/util.h> +#include <FspGuids.h> +#include <memrange.h> +#include <stdint.h> void memmap_stash_early_dram_usage(void) { @@ -27,3 +32,50 @@ return e; } + +/* + * For data stored in TSEG, ensure TValid is clear so R/W access can reach + * the DRAM when not in SMM. + */ +static void clear_tvalid(void) +{ + msr_t hwcr = rdmsr(HWCR_MSR); + msr_t mask = rdmsr(SMM_MASK_MSR); + int tvalid = !!(mask.lo & SMM_TSEG_VALID); + + if (hwcr.lo & SMM_LOCK) { + if (!tvalid) /* not valid but locked means still accessible */ + return; + + printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); + return; + } + + mask.lo &= ~SMM_TSEG_VALID; + wrmsr(SMM_MASK_MSR, mask); +} + +void smm_region(uintptr_t *start, size_t *size) +{ + static int once; + struct range_entry tseg; + int status; + + *start = 0; + *size = 0; + + status = fsp_find_range_hob(&tseg, AMD_FSP_TSEG_HOB_GUID.b); + + if (status < 0) { + printk(BIOS_ERR, "Error: unable to find TSEG HOB\n"); + return; + } + + *start = (uintptr_t)range_entry_base(&tseg); + *size = range_entry_size(&tseg); + + if (!once) { + clear_tvalid(); + once = 1; + } +} diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 8424d46..970d1373d 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -3,60 +3,11 @@ #include <assert.h> #include <stdint.h> #include <console/console.h> -#include <cpu/x86/smm.h> -#include <cpu/amd/msr.h> #include <arch/bert_storage.h> #include <memrange.h> #include <fsp/util.h> #include <FspGuids.h> -/* - * For data stored in TSEG, ensure TValid is clear so R/W access can reach - * the DRAM when not in SMM. - */ -static void clear_tvalid(void) -{ - msr_t hwcr = rdmsr(HWCR_MSR); - msr_t mask = rdmsr(SMM_MASK_MSR); - int tvalid = !!(mask.lo & SMM_TSEG_VALID); - - if (hwcr.lo & SMM_LOCK) { - if (!tvalid) /* not valid but locked means still accessible */ - return; - - printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); - return; - } - - mask.lo &= ~SMM_TSEG_VALID; - wrmsr(SMM_MASK_MSR, mask); -} - -void smm_region(uintptr_t *start, size_t *size) -{ - static int once; - struct range_entry tseg; - int status; - - *start = 0; - *size = 0; - - status = fsp_find_range_hob(&tseg, AMD_FSP_TSEG_HOB_GUID.b); - - if (status < 0) { - printk(BIOS_ERR, "Error: unable to find TSEG HOB\n"); - return; - } - - *start = (uintptr_t)range_entry_base(&tseg); - *size = range_entry_size(&tseg); - - if (!once) { - clear_tvalid(); - once = 1; - } -} - void bert_reserved_region(void **start, size_t *size) { struct range_entry bert; -- To view, visit https://review.coreboot.org/c/coreboot/+/50400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45 Gerrit-Change-Number: 50400 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncar
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50400 ) Change subject: soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncar ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/cpu/noncar/memmap.c: https://review.coreboot.org/c/coreboot/+/50400/comment/ad5a57d1_d6e1c552 PS2, Line 40: clear_tvalid > Out of scope for this patch but I believe this is common for all our products so it could also be co […] yes, it can be commonized for everything in soc/amd. i'll prepare a patch soon-ish -- To view, visit https://review.coreboot.org/c/coreboot/+/50400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45 Gerrit-Change-Number: 50400 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 19:15:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/hid: Enforce level triggered IRQ mode
by Furquan Shaikh (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Tim Wawrzynczak, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50442 ) Change subject: drivers/i2c/hid: Enforce level triggered IRQ mode ...................................................................... Patch Set 2: (1 comment) File src/drivers/i2c/hid/hid.c: https://review.coreboot.org/c/coreboot/+/50442/comment/ffa22d61_94426fa3 PS2, Line 79: dev->enabled = 0; > I can update the IRQ mode to use LEVEL triggered with a warning. But if the HID device is not really following the specification, won't updating the IRQ mode mask the issue and lead to undefined behavior until someone notices the warning? That is true. Setting enabled to 0 does force the user to pay attention to the error in BIOS logs. Before we do that, we should ensure that all the current users of i2c/hid driver are actually setting the irq line to level triggered. -- To view, visit https://review.coreboot.org/c/coreboot/+/50442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Gerrit-Change-Number: 50442 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 19:14:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/fsp/cezanne: add FspGuids.h
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50402 ) Change subject: vc/amd/fsp/cezanne: add FspGuids.h ...................................................................... vc/amd/fsp/cezanne: add FspGuids.h Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I54579a7998d1a4a232cb5286d3f481e2e63a4476 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50402 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/vendorcode/amd/fsp/cezanne/FspGuids.h 1 file changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/vendorcode/amd/fsp/cezanne/FspGuids.h b/src/vendorcode/amd/fsp/cezanne/FspGuids.h new file mode 100644 index 0000000..7f7a91d --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/FspGuids.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __FSP_GUIDS__ +#define __FSP_GUIDS__ + +#include <uuid.h> + +#define AMD_FSP_TSEG_HOB_GUID \ + GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \ + 0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c) + +#define AMD_FSP_BERT_HOB_GUID \ + GUID_INIT(0xa21f7ab5, 0x6a89, 0x4df2, \ + 0xb9, 0x19, 0x51, 0xad, 0x95, 0x50, 0x5b, 0xd8) + +#endif /* __FSP_GUIDS__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54579a7998d1a4a232cb5286d3f481e2e63a4476 Gerrit-Change-Number: 50402 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50399 ) Change subject: soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__ ...................................................................... soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__ No PCI or PNP functions are used in here. TEST=Timeless build results in identical image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50399 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/memmap.c 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 04c2fd8..8424d46 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#define __SIMPLE_DEVICE__ - #include <assert.h> #include <stdint.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812 Gerrit-Change-Number: 50399 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50399 ) Change subject: soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__ ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Hmm, we've been carrying that around for a long time. iirc in some chipset before stoneyridge that was actually used -- To view, visit https://review.coreboot.org/c/coreboot/+/50399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812 Gerrit-Change-Number: 50399 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 19:12:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/memmap: drop __SIMPLE_DEVICE__
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50398 ) Change subject: soc/amd/stoneyridge/memmap: drop __SIMPLE_DEVICE__ ...................................................................... soc/amd/stoneyridge/memmap: drop __SIMPLE_DEVICE__ No PCI or PNP functions are used in here. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I46851656db1f1866a82f06ceab67c93019cc6af1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50398 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/stoneyridge/memmap.c 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 67a4319..32790ec 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#define __SIMPLE_DEVICE__ - #include <assert.h> #include <stdint.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46851656db1f1866a82f06ceab67c93019cc6af1 Gerrit-Change-Number: 50398 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021