coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: tests: Add lib/stack-test test case
by Paul Fagerburg (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Martin Roth, jacz(a)semihalf.com, Jan Dabros. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50305 ) Change subject: tests: Add lib/stack-test test case ...................................................................... Patch Set 2: (1 comment) File tests/lib/stack-test.c: https://review.coreboot.org/c/coreboot/+/50305/comment/27d79151_481d8998 PS1, Line 102: stack[i] = 0x42420707; > I do not think that size being even or odd changes anything in this situation. […] I agree, the stack is almost always an even number of machine words, often a power of 2. But it's not a requirement, and I don't want the unit test to fail later when the stack size happens to be an odd number of machine words because I suggested an optimization in a unit test. That was a bad suggestion, so I prefer that it gets undone. The other option is to add a test_assert at the start of the test to check if the stack size is an even number of machine words. -- To view, visit https://review.coreboot.org/c/coreboot/+/50305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf0cceac290618a50ecc4e65f1f9551dbf31bd32 Gerrit-Change-Number: 50305 Gerrit-PatchSet: 2 Gerrit-Owner: jacz(a)semihalf.com Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: jacz(a)semihalf.com Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 18:47:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: jacz(a)semihalf.com Comment-In-Reply-To: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/hid: Enforce level triggered IRQ mode
by Furquan Shaikh (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Tim Wawrzynczak, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50442 ) Change subject: drivers/i2c/hid: Enforce level triggered IRQ mode ...................................................................... Patch Set 2: (1 comment) File src/drivers/i2c/hid/hid.c: https://review.coreboot.org/c/coreboot/+/50442/comment/56cb36ba_33163802 PS2, Line 79: dev->enabled = 0; Rather than setting device to disabled, would it make sense to print the warning and update the irq mode to use LEVEL triggered? We can add a runtime assert, but generally, I think it is not a graceful way of handling a component that is not really critical for boot. Also, there are two irq configs -- irq and irq_gpio. Probably need to check which is actually being used by the board first? -- To view, visit https://review.coreboot.org/c/coreboot/+/50442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Gerrit-Change-Number: 50442 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 18:44:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Benjamin Doron (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Michael Niewöhner. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49140/comment/b7981edf_8abced98 PS3, Line 11: > Not needed. SlpS0 is not asserted externally but by the SoC. And the pad doesn't need to be `_NF`? > So, the problem seems to be that Linux doesn't differentiate PC10-only and PC10+SlpS0 systems. Iow. there's a check missing here ... https://github.com/torvalds/linux/blob/master/drivers/platform/x86/intel_pm… Well, ideally the system would make it to SlpS0. I think it's correct to warn that this didn't happen. However, if the table doesn't advertise support, it can be argued that the kernel doesn't need to check the default address... To me, this appears deliberate, but I couldn't be sure. > Hmm, somewhere above you wrote Linux prints an error for PC10 on vendor firmware. Did you really mean PC10 or SlpS0? I meant PC10. Are ASPM and L1 substates involved? The vendor firmware has the "ASPM not supported" bit set in FADT and disables L1 substates. In coreboot, I had disabled L1 substates and set ASPM to "L1" on the WLAN's root port to mitigate AER errors. I noticed now that the LAN's root port has disabled ASPM but I'm not sure why (the bit is read-write-once, I'll look into that). -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 09 Feb 2021 18:43:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI
by Raul Rangel (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50344 ) Change subject: soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > From what I can see: […] I just pushed a patch chain that moves them to soc. -- To view, visit https://review.coreboot.org/c/coreboot/+/50344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732 Gerrit-Change-Number: 50344 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 18:40:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/blocks/lpc: Remove common SPI registers
by Raul Rangel (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50446 ) Change subject: soc/amd/common/blocks/lpc: Remove common SPI registers ...................................................................... soc/amd/common/blocks/lpc: Remove common SPI registers Use the SoC versions instead. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0 --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/common/block/lpc/lpc_util.c M src/soc/amd/common/block/spi/fch_spi.c 4 files changed, 4 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/50446/1 diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index fbedb71..4e2660b 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -113,15 +113,6 @@ #define LPC_WIDEIO2_GENERIC_PORT 0x90 -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 -#define SPI_BASE_ALIGNMENT BIT(6) -#define SPI_BASE_RESERVED (BIT(4) | BIT(5)) -#define ROUTE_TPM_2_SPI BIT(3) -#define SPI_ABORT_ENABLE BIT(2) -#define SPI_ROM_ENABLE BIT(1) -#define SPI_ROM_ALT_ENABLE BIT(0) -#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) - /* LPC register 0xb8 is DWORD, here there are definitions for byte access. For example, bits 31-24 are accessed through byte access at register 0xbb. */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 7f3bea0..d68814b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -16,8 +16,9 @@ #include <amdblocks/espi.h> #include <amdblocks/lpc.h> #include <soc/acpi.h> -#include <soc/southbridge.h> #include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/southbridge.h> /* Most systems should have already enabled the bridge */ void __weak soc_late_lpc_bridge_enable(void) { } diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index eb129dc..fb231dd 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -8,6 +8,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/lpc.h> #include <soc/iomap.h> +#include <soc/lpc.h> #include <soc/southbridge.h> /* The LPC-ISA bridge is always at D14F3 */ diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index c39147a..a644d27 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -6,6 +6,7 @@ #include <arch/mmio.h> #include <console/console.h> #include <soc/iomap.h> +#include <soc/lpc.h> #include <stdint.h> static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm) -- To view, visit https://review.coreboot.org/c/coreboot/+/50446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0 Gerrit-Change-Number: 50446 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Add SPI registers
by Raul Rangel (Code Review) 09 Feb '21

09 Feb '21

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Change in coreboot[master]: soc/amd/picasso: Add SPI registers
by Raul Rangel (Code Review) 09 Feb '21

09 Feb '21

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Change in coreboot[master]: soc/amd/stoneyridge: Add SPI registers
by Raul Rangel (Code Review) 09 Feb '21

09 Feb '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50443 ) Change subject: soc/amd/stoneyridge: Add SPI registers ...................................................................... soc/amd/stoneyridge: Add SPI registers This is a copy/paste of amdblocks/lpc.h. The registers are different for picasso and cezanne, so I'm moving them to soc. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e --- A src/soc/amd/stoneyridge/include/soc/lpc.h 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/50443/1 diff --git a/src/soc/amd/stoneyridge/include/soc/lpc.h b/src/soc/amd/stoneyridge/include/soc/lpc.h new file mode 100644 index 0000000..55e39cc --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/lpc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_STONEYRIDGE_LPC_H +#define AMD_STONEYRIDGE_LPC_H + +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(6) +#define SPI_BASE_RESERVED (BIT(4) | BIT(5)) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +#endif /* AMD_STONEYRIDGE_LPC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e Gerrit-Change-Number: 50443 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/hid: Enforce level triggered IRQ mode
by Karthik Ramasubramanian (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50442 ) Change subject: drivers/i2c/hid: Enforce level triggered IRQ mode ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/50442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Gerrit-Change-Number: 50442 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 18:26:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/selfboot.c: Fix indentation and drop one newline
by HAOUAS Elyes (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Nico Huber, Angel Pons, Julius Werner, Arthur Heymans. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50397 ) Change subject: lib/selfboot.c: Fix indentation and drop one newline ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica4254297f5d05e75f852d7e9a9e7bb833dfcea7 Gerrit-Change-Number: 50397 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 09 Feb 2021 17:59:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021