coreboot-gerrit February 2021

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Change in coreboot[master]: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID...
by Karthik Ramasubramanian (Code Review) 09 Feb '21

09 Feb '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50453 ) Change subject: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C ...................................................................... mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3… BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/50453/1 diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 44b3523..a358fb8 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -191,7 +191,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end -- To view, visit https://review.coreboot.org/c/coreboot/+/50453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7 Gerrit-Change-Number: 50453 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C
by Karthik Ramasubramanian (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jeremy Soller. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50452 ) Change subject: mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C ...................................................................... mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3… BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/system76/lemp9/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/50452/1 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 3a0758a..263036d 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -97,7 +97,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN040D"" register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 15 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/50452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606 Gerrit-Change-Number: 50452 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/hid: Enforce level triggered IRQ mode
by Karthik Ramasubramanian (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Tim Wawrzynczak, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50442 to look at the new patch set (#3). Change subject: drivers/i2c/hid: Enforce level triggered IRQ mode ...................................................................... drivers/i2c/hid: Enforce level triggered IRQ mode As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. This change ensures that the IRQ is appropriately configured. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3… BUG=b:172846122 TEST=./util/abuild/abuild. Build and boot to OS in Dedede. Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/drivers/i2c/hid/hid.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/50442/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Gerrit-Change-Number: 50442 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Add PCI IRQ Router definitions
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50451 ) Change subject: soc/amd/cezanne: Add PCI IRQ Router definitions ...................................................................... Patch Set 1: (2 comments) File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/50451/comment/35cf608c_dfdcad88 PS1, Line 30: select SOC_AMD_COMMON_BLOCK_PCI_MMCONF you can drop this, since SOC_AMD_COMMON_BLOCK_PCI already selects SOC_AMD_COMMON_BLOCK_PCI_MMCONF File src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h: https://review.coreboot.org/c/coreboot/+/50451/comment/bafae8c0_6ba2e0d5 PS1, Line 61: #define PIRQ_UART2 0x78 /* UART2 */ : #define PIRQ_UART3 0x79 /* UART3 */ without having verified this, this smells wrong. not sure if the documentation fixes in area around that uarts are already in a ppr release -- To view, visit https://review.coreboot.org/c/coreboot/+/50451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e Gerrit-Change-Number: 50451 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 22:02:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/cpu: move set_cstate_io_addr to common code
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50407 ) Change subject: soc/amd/picasso/cpu: move set_cstate_io_addr to common code ...................................................................... soc/amd/picasso/cpu: move set_cstate_io_addr to common code Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3b8a38ea39d8dc56ff1249a3212fe352b3e805ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/50407 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/cpu/noncar/cpu.c M src/soc/amd/common/block/include/amdblocks/cpu.h M src/soc/amd/picasso/cpu.c 3 files changed, 13 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index 7c1daf9..98926bf 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -2,8 +2,20 @@ #include <amdblocks/cpu.h> #include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> +#include <soc/iomap.h> int get_cpu_count(void) { return 1 + (cpuid_ecx(0x80000008) & 0xff); } + +void set_cstate_io_addr(void) +{ + msr_t cst_addr; + + cst_addr.hi = 0; + cst_addr.lo = ACPI_CPU_CONTROL; + wrmsr(MSR_CSTATE_ADDRESS, cst_addr); +} diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index 50300d5..0627bc1 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -4,6 +4,7 @@ #define AMD_BLOCK_CPU_H int get_cpu_count(void); +void set_cstate_io_addr(void); void write_resume_eip(void); #endif /* AMD_BLOCK_CPU_H */ diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index b18a3b4..9460485 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -42,15 +42,6 @@ x86_mtrr_check(); } -static void set_cstate_io_addr(void) -{ - msr_t cst_addr; - - cst_addr.hi = 0; - cst_addr.lo = ACPI_CPU_CONTROL; - wrmsr(MSR_CSTATE_ADDRESS, cst_addr); -} - static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; -- To view, visit https://review.coreboot.org/c/coreboot/+/50407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b8a38ea39d8dc56ff1249a3212fe352b3e805ce Gerrit-Change-Number: 50407 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Nico Huber, Benjamin Doron, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50048 ) Change subject: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/50048/comment/f592ef08_3eb7a8f9 PS5, Line 332: } > Perhaps the chipset is fairly well locked-down, but currently, coreboot has no SPI protection. In that regard, CHIPSET_LOCKDOWN_FSP could be superior. Security that relies on blobs doing its job right is never going to be superior. -- To view, visit https://review.coreboot.org/c/coreboot/+/50048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab97f545597388d9c4811b5baac82d3e06d86484 Gerrit-Change-Number: 50048 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:55:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration
by Benjamin Doron (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50048 ) Change subject: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/50048/comment/7156ee0d_d8894eeb PS5, Line 332: } > > How broken is it? Later platforms define the else case. > > I don't know. I didn't look into it in years. I guess everybody just > runs `chipsec` before releasing anything and fixes things up on local > branches (or maybe master too). What I seem to remember from the review > when the chipset_lockdown distinction was first implemented: > > Me: This and that is broken on the CHIPSET_LOCKDOWN_FSP path. > Intel: But we set CHIPSET_LOCKDOWN_COREBOOT for all boards in the tree. > > See how much they care about security? I don't remember if things were > fixed or if I just gave up reviewing. It was a mess and I don't know > if CHIPSET_LOCKDOWN_FSP ever made sense / worked properly. Perhaps the chipset is fairly well locked-down, but currently, coreboot has no SPI protection. In that regard, CHIPSET_LOCKDOWN_FSP could be superior. > It depends on the binary. With the current state of this patch, a > binary that defaults to not locking, and coreboot configured to > CHIPSET_LOCKDOWN_FSP, security can be compromised. Maybe > more than without this patch, I guess one needs to read all > the involved code to tell. I suppose that could be the case in some instances, and it definitely would be a concern. I will define the else case and set CHIPSET_LOCKDOWN_COREBOOT for the two boards I mentioned. Then, perhaps CHIPSET_LOCKDOWN_FSP should be dropped entirely. > IMHO, it's easier to drop support for FSP lockdown. Has anybody ever expressed interest in it? -- To view, visit https://review.coreboot.org/c/coreboot/+/50048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab97f545597388d9c4811b5baac82d3e06d86484 Gerrit-Change-Number: 50048 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:51:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add PCI IRQ Router definitions
by Raul Rangel (Code Review) 09 Feb '21

09 Feb '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50451 ) Change subject: soc/amd/cezanne: Add PCI IRQ Router definitions ...................................................................... soc/amd/cezanne: Add PCI IRQ Router definitions These definitions were identical to picasso. The only thing I changed was that I renamed Misc1 and Misc2 to HPET_L and HPET_H. This change still doesn't write the PCI_IRQ register for all the PCI devices. We need to refactor the picasso pci_gpp code first. TEST=Boot majolica and see FCH IRQs being programmed. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/fch.c A src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h 3 files changed, 140 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/50451/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index a881ef8..25d703a 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -26,6 +26,7 @@ select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_NONCAR + select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select SOC_AMD_COMMON_BLOCK_SMBUS diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 5fb4f0a..c945982 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -1,10 +1,72 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> +#include <amdblocks/amd_pci_util.h> #include <assert.h> +#include <bootstate.h> +#include <soc/amd_pci_int_defs.h> #include <soc/iomap.h> #include <soc/southbridge.h> +/* + * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME + * provides a visible association with the index, therefore helping + * maintainability of table. If a new index/name is defined in + * amd_pci_int_defs.h, just add the pair at the end of this table. + * Order is not important. + */ +const static struct irq_idx_name irq_association[] = { + { PIRQ_A, "INTA#" }, + { PIRQ_B, "INTB#" }, + { PIRQ_C, "INTC#" }, + { PIRQ_D, "INTD#" }, + { PIRQ_E, "INTE#" }, + { PIRQ_F, "INTF#/GENINT2" }, + { PIRQ_G, "INTG#" }, + { PIRQ_H, "INTH#" }, + { PIRQ_MISC, "Misc" }, + { PIRQ_MISC0, "Misc0" }, + { PIRQ_HPET_L, "HPET_L" }, + { PIRQ_HPET_H, "HPET_H" }, + { PIRQ_SIRQA, "Ser IRQ INTA" }, + { PIRQ_SIRQB, "Ser IRQ INTB" }, + { PIRQ_SIRQC, "Ser IRQ INTC" }, + { PIRQ_SIRQD, "Ser IRQ INTD" }, + { PIRQ_SCI, "SCI" }, + { PIRQ_SMBUS, "SMBUS" }, + { PIRQ_ASF, "ASF" }, + { PIRQ_PMON, "PerMon" }, + { PIRQ_SD, "SD" }, + { PIRQ_SDIO, "SDIO" }, + { PIRQ_CIR, "CIR" }, + { PIRQ_GPIOA, "GPIOa" }, + { PIRQ_GPIOB, "GPIOb" }, + { PIRQ_GPIOC, "GPIOc" }, + { PIRQ_SATA, "SATA" }, + { PIRQ_EMMC, "eMMC" }, + { PIRQ_GPP0, "GPP0" }, + { PIRQ_GPP1, "GPP1" }, + { PIRQ_GPP2, "GPP2" }, + { PIRQ_GPP3, "GPP3" }, + { PIRQ_GPIO, "GPIO" }, + { PIRQ_I2C0, "I2C0" }, + { PIRQ_I2C1, "I2C1" }, + { PIRQ_I2C2, "I2C2" }, + { PIRQ_I2C3, "I2C3" }, + { PIRQ_UART0, "UART0" }, + { PIRQ_UART1, "UART1" }, + { PIRQ_I2C4, "I2C4" }, + { PIRQ_I2C5, "I2C5" }, + { PIRQ_UART2, "UART2" }, + { PIRQ_UART3, "UART3" }, +}; + +const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) +{ + *size = ARRAY_SIZE(irq_association); + return irq_association; +} + static void fch_init_acpi_ports(void) { /* We use some of these ports in SMM regardless of whether or not @@ -38,3 +100,15 @@ void fch_final(void *chip_info) { } + +static void set_pci_irqs(void *unused) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); +} + +/* + * Hook this function into the PCI state machine + * on entry into BS_DEV_ENABLE. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); diff --git a/src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h b/src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h new file mode 100644 index 0000000..c0c4cd1 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_AMD_PCI_INT_DEFS_H +#define AMD_CEZANNE_AMD_PCI_INT_DEFS_H + +/* + * PIRQ and device routing - these define the index into the + * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. + */ + +#define PIRQ_NC 0x1f /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_HPET_L 0x0a /* HPET CONF_CAP_H[0:7] */ +#define PIRQ_HPET_H 0x0b /* HPET CONF_CAP_H[15:8] */ +#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS */ +#define PIRQ_ASF 0x12 /* ASF */ +/* 0x13-0x15 reserved */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +#define PIRQ_SD 0x17 /* SD */ +/* 0x18-0x19 reserved */ +#define PIRQ_SDIO 0x1a /* SDIO */ +/* 0x1b-0x1f reserved */ +#define PIRQ_CIR 0x20 /* CIR, no IRQ connected */ +#define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ +#define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ +#define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ +/* 0x24-0x40 reserved */ +#define PIRQ_SATA 0x41 /* SATA */ +/* 0x42 reserved */ +#define PIRQ_EMMC 0x43 /* eMMC */ +/* 0x44-0x4f reserved */ +#define PIRQ_GPP0 0x50 /* GPPInt0 */ +#define PIRQ_GPP1 0x51 /* GPPInt1 */ +#define PIRQ_GPP2 0x52 /* GPPInt2 */ +#define PIRQ_GPP3 0x53 /* GPPInt3 */ +/* 0x54-0x61 reserved */ +#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +/* 0x63-0x6f reserved */ +#define PIRQ_I2C0 0x70 /* I2C0 */ +#define PIRQ_I2C1 0x71 /* I2C1 */ +#define PIRQ_I2C2 0x72 /* I2C2 */ +#define PIRQ_I2C3 0x73 /* I2C3 */ +#define PIRQ_UART0 0x74 /* UART0 */ +#define PIRQ_UART1 0x75 /* UART1 */ +#define PIRQ_I2C4 0x76 /* I2C4 */ +#define PIRQ_I2C5 0x77 /* I2C5 */ +#define PIRQ_UART2 0x78 /* UART2 */ +#define PIRQ_UART3 0x79 /* UART3 */ +/* 0x7a-0x7f reserved */ + +#endif /* AMD_CEZANNE_AMD_PCI_INT_DEFS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e Gerrit-Change-Number: 50451 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: soc/intel/fsp_broadwell_de: Use smm_module_loaderv2
by Stefan Reinauer (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Marc Jones, Jay Talbott, Patrick Rudolph. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50314 ) Change subject: soc/intel/fsp_broadwell_de: Use smm_module_loaderv2 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I3a6e17e8590a2af9b4e7c701f8fccfccfa3ea94b Gerrit-Change-Number: 50314 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:38:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: cpu/x86/smm: Introduce SMM module loader version 2
by Stefan Reinauer (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Marc Jones, Martin Roth, Jay Talbott, Rocky Phagura. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50313 ) Change subject: cpu/x86/smm: Introduce SMM module loader version 2 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I76bb506de56c816f6c0635bfd990125b789c5877 Gerrit-Change-Number: 50313 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 21:37:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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