coreboot-gerrit February 2021

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Change in coreboot[master]: security/tpm: Add crypto agility support
by build bot (Jenkins) (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Frans Hendriks, Christian Walter, Aaron Durbin, Wim Vervoorn. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50054 ) Change subject: security/tpm: Add crypto agility support ...................................................................... Patch Set 1: (9 comments) File src/security/tpm/tspi/tspi.c: https://review.coreboot.org/c/coreboot/+/50054/comment/8bd09c8c_f203b57a PS1, Line 227: <<<<<<< HEAD (567e8e Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030") space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/50054/comment/0e2e1ab1_2d4b1c89 PS1, Line 227: <<<<<<< HEAD (567e8e Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030") spaces required around that '<' (ctx:OxW) https://review.coreboot.org/c/coreboot/+/50054/comment/1493538b_9aed90c0 PS1, Line 234: ======= spaces required around that '==' (ctx:ExO) https://review.coreboot.org/c/coreboot/+/50054/comment/e50c0b38_6f1883ee PS1, Line 234: ======= spaces required around that '==' (ctx:OxO) https://review.coreboot.org/c/coreboot/+/50054/comment/51cc646e_9141aa4e PS1, Line 234: ======= spaces required around that '==' (ctx:OxO) https://review.coreboot.org/c/coreboot/+/50054/comment/73298578_70318988 PS1, Line 234: ======= spaces required around that '=' (ctx:OxE) https://review.coreboot.org/c/coreboot/+/50054/comment/22268581_928bbcbf PS1, Line 254: >>>>>>> CHANGE (1474dd security/tpm: Add crypto agility support) space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/50054/comment/7658693d_bf394e36 PS1, Line 254: >>>>>>> CHANGE (1474dd security/tpm: Add crypto agility support) spaces required around that '>' (ctx:OxW) https://review.coreboot.org/c/coreboot/+/50054/comment/314b1d03_db5bb724 PS1, Line 254: >>>>>>> CHANGE (1474dd security/tpm: Add crypto agility support) spaces required around that ':' (ctx:VxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/50054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc8d994081896e8c0d511c31e9741297227afef Gerrit-Change-Number: 50054 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 23:12:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/tpm: Add crypto agility support
by Philipp Deppenwiese (Code Review) 10 Feb '21

10 Feb '21

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50054 ) Change subject: security/tpm: Add crypto agility support ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/50054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc8d994081896e8c0d511c31e9741297227afef Gerrit-Change-Number: 50054 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 23:12:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google: order matters in mem_parts_used.txt
by Rob Barnes (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Furquan Shaikh, Paul Fagerburg. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50449 ) Change subject: mb/google: order matters in mem_parts_used.txt ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS1: > I updated the ones for dedede and volteer. […] The comment still makes sense. You can mix and match assigned and unassigned ids. The order of the unassigned ids is what matters. Thanks for pushing this through. +2. -- To view, visit https://review.coreboot.org/c/coreboot/+/50449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02 Gerrit-Change-Number: 50449 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 23:02:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Fagerburg <pfagerburg(a)chromium.org> Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add empty SMM-handler
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50455 ) Change subject: soc/amd/cezanne: add empty SMM-handler ...................................................................... soc/amd/cezanne: add empty SMM-handler Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I95908fac3b1e17a16542e5d80001fac3d22d839a --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/smihandler.c 3 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/50455/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index a881ef8..6e844c2 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -16,6 +16,7 @@ select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA select HAVE_CF9_RESET + select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select IOAPIC select PLATFORM_USES_FSP2_0 @@ -131,6 +132,19 @@ default 0xfedc9000 if UART_FOR_CONSOLE = 0 default 0xfedca000 if UART_FOR_CONSOLE = 1 +config SMM_TSEG_SIZE + hex + default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER + default 0x0 + +config SMM_RESERVED_SIZE + hex + default 0x180000 + +config SMM_MODULE_STACK_SIZE + hex + default 0x800 + menu "PSP Configuration Options" config AMD_FWM_POSITION_INDEX diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index ce9f66c..3501282 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -4,6 +4,7 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm # Beware that all-y also adds the compilation unit to verstage on PSP all-y += config.c @@ -34,6 +35,8 @@ ramstage-y += root_complex.c ramstage-y += uart.c +smm-y += smihandler.c + CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c new file mode 100644 index 0000000..2d9e487 --- /dev/null +++ b/src/soc/amd/cezanne/smihandler.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/smm.h> + +void southbridge_smi_handler(void) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95908fac3b1e17a16542e5d80001fac3d22d839a Gerrit-Change-Number: 50455 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030"
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50052 ) Change subject: Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030" ...................................................................... Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030" This reverts commit 75f6ab35ffefec72e343175686d7ef45b30b0939. Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030. This causes an issue where the WP pin is not recognized. BUG=b:179320024 TEST=WP pin shows up properly in crossystem after reverting this change. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I0850fd085b5ee70522752633900f69d4d3732321 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50052 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/include/soc/gpio.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index f76c446..0f4507c 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -3,7 +3,7 @@ #ifndef AMD_PICASSO_GPIO_H #define AMD_PICASSO_GPIO_H -#define GPIO_DEVICE_NAME "AMDI0030" +#define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" #ifndef __ACPI__ -- To view, visit https://review.coreboot.org/c/coreboot/+/50052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0850fd085b5ee70522752633900f69d4d3732321 Gerrit-Change-Number: 50052 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Nico Huber, Benjamin Doron, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50048 ) Change subject: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/50048/comment/696a53fc_2237c523 PS5, Line 332: } > > > Perhaps the chipset is fairly well locked-down, but currently, coreboot has no SPI protection. […] Yeah, I'm working on it. -- To view, visit https://review.coreboot.org/c/coreboot/+/50048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab97f545597388d9c4811b5baac82d3e06d86484 Gerrit-Change-Number: 50048 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 22:36:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports
by Felix Held (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50454 to look at the new patch set (#2). Change subject: soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports ...................................................................... soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114 --- M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/include/soc/southbridge.h 2 files changed, 28 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50454/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114 Gerrit-Change-Number: 50454 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration
by Benjamin Doron (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50048 ) Change subject: soc/intel/{skylake,cannonlake}: Co-ordinate lockdown configuration ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/50048/comment/3ab9e968_63868e4e PS5, Line 332: } > > Perhaps the chipset is fairly well locked-down, but currently, coreboot has no SPI protection. In that regard, CHIPSET_LOCKDOWN_FSP could be superior. > > Security that relies on blobs doing its job right is never going to be superior. I meant that the feature would be configured. Regardless, see CB:40830. -- To view, visit https://review.coreboot.org/c/coreboot/+/50048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab97f545597388d9c4811b5baac82d3e06d86484 Gerrit-Change-Number: 50048 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 22:31:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports
by build bot (Jenkins) (Code Review) 09 Feb '21

09 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50454 ) Change subject: soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/fch.c: https://review.coreboot.org/c/coreboot/+/50454/comment/7e9c3d33_41fa2f1a PS1, Line 29: /* trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/50454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114 Gerrit-Change-Number: 50454 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Feb 2021 22:28:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Benjamin Doron (Code Review) 09 Feb '21

09 Feb '21

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49140/comment/bf8dd384_36775c4c PS3, Line 11: > Hmmm... just curious, what kernel version exactly? There was some fix recently that should be in mainline or maybe even stable. I've been using 5.7.17, but it's the source code of 5.11.0-rc7 and master that I looked at. Commit Message: https://review.coreboot.org/c/coreboot/+/49140/comment/dd744f8c_6bf51958 PS5, Line 9: > maybe add "It is required to make the kernel load `intel_pmc_core`. […] Done, thanks. https://review.coreboot.org/c/coreboot/+/49140/comment/aaddb14e_115b92b5 PS5, Line 13: predictably. > ... via debugfs. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Feb 2021 22:28:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit February 2021