coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

1 participants
7192 discussions

Change in coreboot[master]: tests: Add acpi/acpigen-test test case
by Name of user not set (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Martin Roth, Paul Fagerburg, Jan Dabros, Duncan Laurie. jacz(a)semihalf.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50520 ) Change subject: tests: Add acpi/acpigen-test test case ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hello. This is WIP version of this test. If you see any way of extending it, please leave a comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/50520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc128212c1f72beb50caca671b4bada3507d3a1f Gerrit-Change-Number: 50520 Gerrit-PatchSet: 1 Gerrit-Owner: jacz(a)semihalf.com Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 12:04:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: tests: Add acpi/acpigen-test test case
by Name of user not set (Code Review) 11 Feb '21

11 Feb '21

jacz(a)semihalf.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50520 ) Change subject: tests: Add acpi/acpigen-test test case ...................................................................... tests: Add acpi/acpigen-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Icc128212c1f72beb50caca671b4bada3507d3a1f --- M tests/Makefile.inc A tests/acpi/Makefile.inc A tests/acpi/acpigen-test.c 3 files changed, 226 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/50520/1 diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 53c0edf..7a15268 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -55,8 +55,8 @@ stages+= ramstage rmodule postcar libagesa alltests:= -subdirs:= tests/arch tests/commonlib tests/console tests/cpu tests/device -subdirs+= tests/drivers tests/ec tests/lib tests/mainboard +subdirs:= tests/arch tests/acpi tests/commonlib tests/console tests/cpu +subdirs+= tests/device tests/drivers tests/ec tests/lib tests/mainboard subdirs+= tests/northbridge tests/security tests/soc tests/southbridge subdirs+= tests/superio tests/vendorcode diff --git a/tests/acpi/Makefile.inc b/tests/acpi/Makefile.inc new file mode 100644 index 0000000..b0ef5fa --- /dev/null +++ b/tests/acpi/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +tests-y += acpigen-test + +acpigen-test-srcs += tests/acpi/acpigen-test.c +acpigen-test-srcs += src/acpi/acpigen.c +acpigen-test-srcs += tests/stubs/console.c diff --git a/tests/acpi/acpigen-test.c b/tests/acpi/acpigen-test.c new file mode 100644 index 0000000..369ff29 --- /dev/null +++ b/tests/acpi/acpigen-test.c @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdlib.h> +#include <types.h> +#include <tests/test.h> +#include <acpi/acpigen.h> + +#define ACPIGEN_TEST_BUFFER_SZ (16 * KiB) + +/* Returns AML package length. Works with normal and extended packages. + This implementation is independent from acpigen.c implementation of package length. */ +static u32 decode_package_length(const char *ptr) +{ + const u8 *aml = (u8 *)ptr; + const u32 offset = (aml[0] == EXT_OP_PREFIX ? 2 : 1); + u32 byte_zero_mask = 0x3F; /* Bits [0:5] */ + u32 byte_count = aml[offset] >> 6; + u32 package_length = 0; + + while (byte_count) { + package_length |= aml[offset + byte_count] << ((byte_count << 3) - 4); + byte_zero_mask = 0x0F; /* Use bits [0:3] of byte 0 */ + byte_count--; + } + + package_length |= (aml[offset] & byte_zero_mask); + + return package_length; +} + +static u32 get_current_block_length(const char *base) +{ + const u32 offset = (base[0] == EXT_OP_PREFIX ? 2 : 1); + + return ((uintptr_t)acpigen_get_current() - ((uintptr_t)base + offset)); +} + +static int setup_acpigen(void **state) +{ + void *buffer = malloc(ACPIGEN_TEST_BUFFER_SZ); + + if (buffer == NULL) + return -1; + + memset(buffer, 0, ACPIGEN_TEST_BUFFER_SZ); + + *state = buffer; + return 0; +} + +static int teardown_acpigen(void **state) +{ + free(*state); + return 0; +} + +static void test_acpigen_single_if(void **state) +{ + char *acpigen_buf = *state; + u32 if_package_length = 0; + u32 block_length = 0; + + acpigen_set_current(acpigen_buf); + + /* Create dummy AML */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 64); + + for (int i = 0; i < 20; ++i) + acpigen_write_store_ops(ZERO_OP, LOCAL1_OP); + + /* Close if */ + acpigen_pop_len(); + + if_package_length = decode_package_length(acpigen_buf); + block_length = get_current_block_length(acpigen_buf); + assert_int_equal(if_package_length, block_length); +} + +static void create_nested_ifs_recursive(char *stack_start[], char *stack_end[], u32 i, u32 n) +{ + if (i >= n) + return; + + stack_start[i] = acpigen_get_current(); + acpigen_write_if_and(LOCAL0_OP, ZERO_OP); + + for (int k = 0; k < 3; ++k) + acpigen_write_store_ops(ZERO_OP, LOCAL1_OP); + + create_nested_ifs_recursive(stack_start, stack_end, i + 1, n); + + acpigen_pop_len(); + stack_end[i] = acpigen_get_current(); +} + +static void test_acpigen_nested_ifs(void **state) +{ + char *acpigen_buf = *state; + const size_t nesting_level = 8; + char *block_start[8] = {0}; + char *block_end[8] = {0}; + + acpigen_set_current(acpigen_buf); + + create_nested_ifs_recursive(block_start, block_end, 0, nesting_level); + + for (int i = 0; i < nesting_level; ++i) + assert_int_equal(decode_package_length(block_start[i]), + block_end[i] - block_start[i] - 1); +} + +static void test_acpigen_write_package(void **state) +{ + char *acpigen_buf = *state; + u32 package_length; + u32 block_length; + + acpigen_set_current(acpigen_buf); + acpigen_write_package(3); + + acpigen_write_return_singleton_buffer(0xA); + acpigen_write_return_singleton_buffer(0x7); + acpigen_write_return_singleton_buffer(0xF); + + acpigen_pop_len(); + + package_length = decode_package_length(acpigen_buf); + block_length = get_current_block_length(acpigen_buf); + assert_int_equal(package_length, block_length); +} + +static void test_acpigen_scope_with_contents(void **state) +{ + char *acpigen_buf = *state; + char *block_start[8] = {0}; + u32 block_counter = 0; + u32 package_length; + u32 block_length; + + acpigen_set_current(acpigen_buf); + + /* Scope("\_SB") { */ + block_start[block_counter++] = acpigen_get_current(); + acpigen_write_scope("\\_SB"); + + /* Device("PCI0") { */ + block_start[block_counter++] = acpigen_get_current(); + acpigen_write_device("PCI0"); + + /* Name(INT1, 0x1234) */ + acpigen_write_name_integer("INT1", 0x1234); + + /* Name (_HID, EisaId ("PNP0A08")) // PCI Express Bus */ + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0A08"); + + /* Method(^BN00, 0, NotSerialized) { */ + block_start[block_counter++] = acpigen_get_current(); + acpigen_write_method("^BN00", 0); + + /* Return( 0x12 + ^PCI0.INT1 ) */ + acpigen_write_return_op(AND_OP); + acpigen_write_byte(0x12); + acpigen_emit_namestring("^PCI0.INT1"); + + /* } */ + acpigen_pop_len(); + block_counter--; + package_length = decode_package_length(block_start[block_counter]); + block_length = get_current_block_length(block_start[block_counter]); + assert_int_equal(package_length, block_length); + + /* Method (_BBN, 0, NotSerialized) { */ + block_start[block_counter++] = acpigen_get_current(); + acpigen_write_method("_BBN", 0); + + /* Return (BN00 ()) */ + acpigen_write_return_namestr("BN00"); + acpigen_emit_byte(0x0A); + + /* } */ + acpigen_pop_len(); + block_counter--; + package_length = decode_package_length(block_start[block_counter]); + block_length = get_current_block_length(block_start[block_counter]); + assert_int_equal(package_length, block_length); + + /* } */ + acpigen_pop_len(); + block_counter--; + package_length = decode_package_length(block_start[block_counter]); + block_length = get_current_block_length(block_start[block_counter]); + assert_int_equal(package_length, block_length); + + /* } */ + acpigen_pop_len(); + block_counter--; + package_length = decode_package_length(block_start[block_counter]); + block_length = get_current_block_length(block_start[block_counter]); + assert_int_equal(package_length, block_length); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup_teardown(test_acpigen_single_if, + setup_acpigen, teardown_acpigen), + cmocka_unit_test_setup_teardown(test_acpigen_nested_ifs, + setup_acpigen, teardown_acpigen), + cmocka_unit_test_setup_teardown(test_acpigen_write_package, + setup_acpigen, teardown_acpigen), + cmocka_unit_test_setup_teardown(test_acpigen_scope_with_contents, + setup_acpigen, teardown_acpigen), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc128212c1f72beb50caca671b4bada3507d3a1f Gerrit-Change-Number: 50520 Gerrit-PatchSet: 1 Gerrit-Owner: jacz(a)semihalf.com Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/{asrock/h110m,intel/kblrvp}: Define `.chipset_lockdown`
by Maxim Polyakov (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Benjamin Doron, Subrata Banik. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50053 ) Change subject: mb/{asrock/h110m,intel/kblrvp}: Define `.chipset_lockdown` ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e263ea7d2b64c9f577998eb3851a1aa1b0902f5 Gerrit-Change-Number: 50053 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 11:49:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/abuild: Ensure that non-Chrome OS builds are non-Chrome OS
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Martin Roth, Julius Werner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50494 ) Change subject: util/abuild: Ensure that non-Chrome OS builds are non-Chrome OS ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb6bcbf3e9ca8cd4ced85c7c9ffaa39505f5a9b7 Gerrit-Change-Number: 50494 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 11:34:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: device: Add unit to Kconfig option name: `PRE_GRAPHICS_DELAY_MS`
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50517 ) Change subject: device: Add unit to Kconfig option name: `PRE_GRAPHICS_DELAY_MS` ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6 Gerrit-Change-Number: 50517 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 11 Feb 2021 11:31:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/cezanne: Fill FADT and MADT
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50510 ) Change subject: soc/amd/cezanne: Fill FADT and MADT ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50510/comment/bd904c08_0c66afc9 PS1, Line 9: configure nit: move to next line File src/soc/amd/cezanne/acpi.c: https://review.coreboot.org/c/coreboot/+/50510/comment/9aa91342_05916067 PS1, Line 85: fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ IIRC the FADT is already zero-initialized. https://review.coreboot.org/c/coreboot/+/50510/comment/acebeef0_5a93057a PS1, Line 100: fadt->x_firmware_ctl_h = 0; src/acpi/acpi.c sets `x_firmware_ctl_l`, and this code overwrites the value. Is this SoC-specific, or is it to comply with the ACPI spec? File src/soc/amd/cezanne/include/soc/acpi.h: https://review.coreboot.org/c/coreboot/+/50510/comment/1a72adf6_39848a05 PS1, Line 9: 0x0D nit: lowercase hex -- To view, visit https://review.coreboot.org/c/coreboot/+/50510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4 Gerrit-Change-Number: 50510 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 11:26:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/cezanne: select ACPI support and make the compiler happy
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50273 ) Change subject: soc/amd/cezanne: select ACPI support and make the compiler happy ...................................................................... Patch Set 4: (2 comments) File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/50273/comment/b753d6bd_a9cf3c4d PS4, Line 19: select HAVE_ACPI_TABLES Why not make SOC_AMD_COMMON_BLOCK_ACPI select this? https://review.coreboot.org/c/coreboot/+/50273/comment/e89f9550_e89b027e PS4, Line 25: select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPI -- To view, visit https://review.coreboot.org/c/coreboot/+/50273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132 Gerrit-Change-Number: 50273 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 11:16:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd: Move southbridge_write_acpi_tables
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50509 ) Change subject: soc/amd: Move southbridge_write_acpi_tables ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/amd/common/block/acpi/tables.c: PS1: nit: rename to `acpi_tables.c`? Or will there be more tables? -- To view, visit https://review.coreboot.org/c/coreboot/+/50509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0 Gerrit-Change-Number: 50509 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Feb 2021 11:13:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common: Fix missing header in amd_pci_utils.h
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50508 ) Change subject: soc/amd/common: Fix missing header in amd_pci_utils.h ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia467c7d6cc0f71580d0b323cb560c444d53bd7f7 Gerrit-Change-Number: 50508 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 11:11:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/spi: Stop using a variable-length array
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Julius Werner, Jacob Garber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50480 ) Change subject: drivers/spi: Stop using a variable-length array ...................................................................... Patch Set 1: (1 comment) File src/drivers/spi/spi_flash.c: https://review.coreboot.org/c/coreboot/+/50480/comment/85b59368_514e7bb6 PS1, Line 95: u8 buff[4 + (1 << DEFAULT_PAGE_SIZE_SHIFT)]; > Hmmm... The problem is that we need to concatenate two buffers. […] I made CB:50519 to avoid having to concatenate buffers inside this function. I'm not sure if it's an improvement, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/50480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib630bff1b496bc276616989d4506a3c96f242e26 Gerrit-Change-Number: 50480 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Comment-Date: Thu, 11 Feb 2021 11:10:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2021