coreboot-gerrit February 2021

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Change in coreboot[master]: haswell: Drop `mainboard_fill_pei_data`
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50538 ) Change subject: haswell: Drop `mainboard_fill_pei_data` ...................................................................... haswell: Drop `mainboard_fill_pei_data` Use global variables to provide mainboard USB settings, and have the northbridge code copy it into the `pei_data` struct. For now. To minimize diffstat noise, this patch does not reindent the now-global mainboard USB configuration arrays. This is cleaned up in a follow-up. Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/google/slippy/variant.h M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/hp/folio_9480m/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/msi/h81m-p33/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/raminit.h M src/northbridge/intel/haswell/romstage.c 16 files changed, 32 insertions(+), 106 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/50538/1 diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 119d007..16f3d0a 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -25,9 +25,7 @@ spd_map[3] = 0xa6; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, @@ -45,7 +43,7 @@ { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { { 1, 0 }, { 1, 0 }, { 1, 1 }, @@ -53,7 +51,3 @@ { 1, 2 }, { 1, 2 }, }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index deb6ec9..b8ecd43 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -23,9 +23,7 @@ spd_map[2] = 0xa4; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, @@ -43,7 +41,7 @@ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* Enable, OCn# */ { 1, 0 }, { 1, 0 }, @@ -52,7 +50,3 @@ { 0, USB_OC_PIN_SKIP }, { 0, USB_OC_PIN_SKIP }, }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index ee14630..f009f5a 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -46,9 +46,7 @@ spd_map[2] = 0xa4; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0064, 1, 0, /* P0: VP8 */ USB_PORT_MINI_PCIE }, @@ -68,14 +66,10 @@ USB_PORT_SKIP }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* Enable, OCn# */ { 1, 0 }, /* P1; CN22 */ { 1, 1 }, /* P2; CN23 */ { 1, 2 }, /* P3; CN25 */ { 1, 2 }, /* P4; CN25 */ }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 7f08a58..fb32b48 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -46,8 +46,3 @@ spd_map[0] = 0xff; spd_map[2] = 0xff; } - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - variant_romstage_entry(pei_data); -} diff --git a/src/mainboard/google/slippy/variant.h b/src/mainboard/google/slippy/variant.h index 2263f9d..bfcf855 100644 --- a/src/mainboard/google/slippy/variant.h +++ b/src/mainboard/google/slippy/variant.h @@ -3,6 +3,4 @@ #ifndef VARIANT_H #define VARIANT_H -void variant_romstage_entry(struct pei_data *pei_data); - #endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 516b26c..de0ac76 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -48,9 +48,7 @@ } } -void variant_romstage_entry(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0064, 1, 0, /* P0: Port A, CN8 */ USB_PORT_BACK_PANEL }, @@ -70,14 +68,10 @@ USB_PORT_INTERNAL }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* Enable, OCn# */ { 1, 0 }, /* P1; Port A, CN8 */ { 1, 0 }, /* P2; Port B, CN9 */ { 0, USB_OC_PIN_SKIP }, /* P3; */ { 0, USB_OC_PIN_SKIP }, /* P4; */ }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index e24dcb9..daf0c16 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -44,9 +44,7 @@ spd_file + (spd_index * spd_len), spd_len); } -void variant_romstage_entry(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, /* P0: Port A, CN10 */ USB_PORT_BACK_PANEL }, @@ -66,14 +64,10 @@ USB_PORT_SKIP }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* Enable, OCn# */ { 1, 0 }, /* P1; Port A, CN10 */ { 1, 2 }, /* P2; Port B, CN11 */ { 0, USB_OC_PIN_SKIP }, /* P3; */ { 0, USB_OC_PIN_SKIP }, /* P4; */ }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 92e1e8d..535c07b 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -62,9 +62,7 @@ } } -void variant_romstage_entry(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ USB_PORT_MINI_PCIE }, @@ -84,14 +82,10 @@ USB_PORT_SKIP }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* Enable, OCn# */ { 1, 0 }, /* P1; Port A, CN6 */ { 0, USB_OC_PIN_SKIP }, /* P2; */ { 0, USB_OC_PIN_SKIP }, /* P3; */ { 0, USB_OC_PIN_SKIP }, /* P4; */ }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index a0b5055..40ff9c2 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -48,9 +48,7 @@ } } -void variant_romstage_entry(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, /* P0: Port A, CN10 */ USB_PORT_BACK_PANEL }, @@ -70,14 +68,10 @@ USB_PORT_SKIP }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* Enable, OCn# */ { 1, 0 }, /* P1; Port A, CN10 */ { 1, 2 }, /* P2; Port B, CN11 */ { 0, USB_OC_PIN_SKIP }, /* P3; */ { 0, USB_OC_PIN_SKIP }, /* P4; */ }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c index 7eeb7bd..0c4308b 100644 --- a/src/mainboard/hp/folio_9480m/romstage.c +++ b/src/mainboard/hp/folio_9480m/romstage.c @@ -23,9 +23,7 @@ spd_map[2] = 0xa4; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */ @@ -36,12 +34,10 @@ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { { 1, USB_OC_PIN_SKIP }, /* dock */ { 1, USB_OC_PIN_SKIP }, /* left */ { 1, USB_OC_PIN_SKIP }, /* right */ { 0, USB_OC_PIN_SKIP }, }; - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 1927517..9c4c9b7 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -49,9 +49,7 @@ spd_map[3] = 0xa6; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ USB_PORT_BACK_PANEL }, @@ -83,7 +81,7 @@ USB_PORT_FRONT_PANEL }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* Enable, OCn# */ { 1, 0 }, /* P1; */ { 1, 0 }, /* P2; */ @@ -92,7 +90,3 @@ { 1, 0 }, /* P6; */ { 1, 0 }, /* P6; */ }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index 3e5cc0d..eaee734 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -46,9 +46,7 @@ spd_map[2] = 0xa2; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ @@ -66,7 +64,7 @@ { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { { 1, 0 }, { 1, 0 }, { 1, USB_OC_PIN_SKIP }, @@ -74,7 +72,3 @@ { 1, 1 }, { 1, 1 }, /* WWAN */ }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c index 6321eeb..56c77cd 100644 --- a/src/mainboard/msi/h81m-p33/romstage.c +++ b/src/mainboard/msi/h81m-p33/romstage.c @@ -23,9 +23,7 @@ spd_map[2] = 0xa4; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, @@ -43,7 +41,7 @@ { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { { 1, 0 }, { 1, 0 }, { 1, 1 }, @@ -51,7 +49,3 @@ { 1, 2 }, { 1, 2 }, }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index c9f1027..a2798d9 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -25,9 +25,7 @@ spd_map[3] = 0xa6; } -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_INTERNAL }, { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, @@ -45,7 +43,7 @@ { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, }; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { /* Enable, OCn# */ { 1, 1 }, { 1, 1 }, @@ -54,7 +52,3 @@ { 1, 3 }, { 1, 3 }, }; - - memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); - memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); -} diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index adf53ea..ee0af77 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -6,15 +6,16 @@ #include <stdint.h> #include "pei_data.h" +/* Mainboard-specific USB configuration */ +extern const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS]; +extern const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS]; + /* Optional function to copy SPD data for on-board memory */ void copy_spd(struct pei_data *peid); /* Mainboard callback to fill in the SPD addresses in MRC format */ void mb_get_spd_map(uint8_t spd_map[4]); -/* Necessary function to initialize pei_data with mainboard-specific settings */ -void mainboard_fill_pei_data(struct pei_data *pei_data); - void sdram_initialize(struct pei_data *pei_data); void setup_sdram_meminfo(struct pei_data *pei_data); int fixup_haswell_errata(void); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index f5d500b2..22489f9 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -18,6 +18,7 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/me.h> +#include <string.h> /* Copy SPD data for on-board memory */ void __weak copy_spd(struct pei_data *peid) @@ -70,7 +71,8 @@ .usb_xhci_on_resume = cfg->usb_xhci_on_resume, }; - mainboard_fill_pei_data(&pei_data); + memcpy(pei_data.usb2_ports, mainboard_usb2_ports, sizeof(mainboard_usb2_ports)); + memcpy(pei_data.usb3_ports, mainboard_usb3_ports, sizeof(mainboard_usb3_ports)); enable_lapic(); -- To view, visit https://review.coreboot.org/c/coreboot/+/50538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e Gerrit-Change-Number: 50538 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [UNTESTED] soc/amd/cezanne/smihandler: add psp_notify_smm call
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

1 0

Change in coreboot[master]: soc/amd: select ACPI_AMD_HARDWARE_SLEEP_VALUES in common ACPI code
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50536 ) Change subject: soc/amd: select ACPI_AMD_HARDWARE_SLEEP_VALUES in common ACPI code ...................................................................... soc/amd: select ACPI_AMD_HARDWARE_SLEEP_VALUES in common ACPI code Change-Id: Ib03c6799017c9f51f3ffac8400c85675ac5d63f1 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig 4 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/50536/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index cc2fd9f..ddc08b9 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -13,7 +13,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select ACPI_AMD_HARDWARE_SLEEP_VALUES select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig index 2b87f18..21961f7 100644 --- a/src/soc/amd/common/block/acpi/Kconfig +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -1,6 +1,7 @@ config SOC_AMD_COMMON_BLOCK_ACPI bool depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO + select ACPI_AMD_HARDWARE_SLEEP_VALUES default n help Select this option to use the AcpiMmio ACPI registers. diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 2a71681..410048f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -16,7 +16,6 @@ select RESET_VECTOR_IN_RAM select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI - select ACPI_AMD_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select DRIVERS_I2C_DESIGNWARE select DRIVERS_USB_PCI_XHCI diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index a1b109e..dcd6b8f 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -9,7 +9,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ACPI_AMD_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH -- To view, visit https://review.coreboot.org/c/coreboot/+/50536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib03c6799017c9f51f3ffac8400c85675ac5d63f1 Gerrit-Change-Number: 50536 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/picasso/psp: move to common code and rename to psp_smm_gen2
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Patrick Georgi, Martin Roth, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50515 to look at the new patch set (#2). Change subject: soc/amd/picasso/psp: move to common code and rename to psp_smm_gen2 ...................................................................... soc/amd/picasso/psp: move to common code and rename to psp_smm_gen2 Change-Id: I771a7d36eea7307754386824190624a09c0e38f7 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/psp/Makefile.inc R src/soc/amd/common/block/psp/psp_smm_gen2.c M src/soc/amd/picasso/Makefile.inc 3 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/50515/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I771a7d36eea7307754386824190624a09c0e38f7 Gerrit-Change-Number: 50515 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: select soc-specific ACPI functionality
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50487 to look at the new patch set (#4). Change subject: soc/amd/cezanne: select soc-specific ACPI functionality ...................................................................... soc/amd/cezanne: select soc-specific ACPI functionality This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be generated for now. There's also no globalnvs.asl that corresponds to nvs.h yet. The added nvs.h has some currently unused fields, but still having them in the struct aligns it with Picasso and also might reduce the noise in future ACPI patches a bit. When most of the ACPI code for Cezanne has landed, we need to do a cleanup though. Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/include/soc/nvs.h M src/soc/amd/cezanne/include/soc/southbridge.h 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/50487/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Gerrit-Change-Number: 50487 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: select soc-specific ACPI functionality
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50487 ) Change subject: soc/amd/cezanne: select soc-specific ACPI functionality ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/cezanne/include/soc/nvs.h: https://review.coreboot.org/c/coreboot/+/50487/comment/6f87695d_997ffd04 PS2, Line 16: uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ : uint8_t lids; /* 0x01 - LID State */ : uint8_t pwrs; /* 0x02 - AC Power State */ : uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ : uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ : uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ : uint8_t tmps; /* 0x17 - Temperature Sensor ID */ : uint8_t tcrt; /* 0x18 - Critical Threshold */ : uint8_t tpsv; /* 0x19 - Passive Threshold */ > no, we dont. it's a copy from picasso right now. […] i've put this on my local todo list for later; i think it would be good to keep cezanne as much aligned to picasso as possible right now. not 100% happy with the unused stuff in here, but keeping it like this will help reducing noise during active development -- To view, visit https://review.coreboot.org/c/coreboot/+/50487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Gerrit-Change-Number: 50487 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 13:28:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Add initial code for adl-m variant board
by Maulik V Vaghela (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Varshit B Pandya, Francois Toguo Fotso, Sridhar Siricilla, Subrata Banik. Maulik V Vaghela has uploaded a new patch set (#22) to the change originally created by Varshit B Pandya. ( https://review.coreboot.org/c/coreboot/+/49871 ) Change subject: mb/intel/adlrvp_m: Add initial code for adl-m variant board ...................................................................... mb/intel/adlrvp_m: Add initial code for adl-m variant board List of changes: 1. Add mainboard Kconfig to Kconfig.name files 2. Handle mainboard names in Kconfig file for adlrvp 3. Add override devicetree for ADL-M RVP. 4. Configure proper PCI and USB ports as per schematics for ADL-M Since ADL-M RVP uses ADL-M PCH, There is difference in number of root ports supported for each. Moving extra ports for ADL-P inside it's overridetree.cb to prevent compilation error. BUG=None BRANCH=None TEST=Able to build ADL-M RVP variants adlrvp_m and adlrvp_m_ext_ec. Signed-0ff-by: Maulik Vaghela <maulik.v.vaghela(a)intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com> Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/devicetree_m.cb A src/mainboard/intel/adlrvp/variants/adlrvp_m/overridetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb 5 files changed, 319 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/49871/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/49871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d Gerrit-Change-Number: 49871 Gerrit-PatchSet: 22 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvm: Add initial code for adl-m variant board
by Maulik V Vaghela (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Varshit B Pandya, Francois Toguo Fotso, Sridhar Siricilla, Subrata Banik. Maulik V Vaghela has uploaded a new patch set (#21) to the change originally created by Varshit B Pandya. ( https://review.coreboot.org/c/coreboot/+/49871 ) Change subject: mb/intel/adlrvm: Add initial code for adl-m variant board ...................................................................... mb/intel/adlrvm: Add initial code for adl-m variant board List of changes: 1. Add mainboard Kconfig to Kconfig.name files 2. Handle mainboard names in Kconfig file for adlrvp 3. Add override devicetree for ADL-M RVP. 4. Configure proper PCI and USB ports as per schematics for ADL-M Since ADL-M RVP uses ADL-M PCH, There is difference in number of root ports supported for each. Moving extra ports for ADL-P inside it's overridetree.cb to prevent compilation error. BUG=None BRANCH=None TEST=Able to build ADL-M RVP variants adlrvp_m and adlrvp_m_ext_ec. Signed-0ff-by: Maulik Vaghela <maulik.v.vaghela(a)intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com> Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/devicetree_m.cb A src/mainboard/intel/adlrvp/variants/adlrvp_m/overridetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb 5 files changed, 319 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/49871/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/49871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d Gerrit-Change-Number: 49871 Gerrit-PatchSet: 21 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP]soc/amd: Remove unused <console/console.h>
by HAOUAS Elyes (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50527 ) Change subject: [WIP]soc/amd: Remove unused <console/console.h> ...................................................................... Patch Set 3: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84cea1a15d1fb220cf95d7ce469728bc6e299685 Gerrit-Change-Number: 50527 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 13:07:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]soc/amd: Remove unused <console/console.h>
by HAOUAS Elyes (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50527 to look at the new patch set (#3). Change subject: [WIP]soc/amd: Remove unused <console/console.h> ...................................................................... [WIP]soc/amd: Remove unused <console/console.h> Change-Id: I84cea1a15d1fb220cf95d7ce469728bc6e299685 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/common/block/pi/refcode_loader.c M src/soc/amd/picasso/early_fch.c M src/soc/amd/picasso/fch.c M src/soc/amd/stoneyridge/memmap.c 5 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/50527/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84cea1a15d1fb220cf95d7ce469728bc6e299685 Gerrit-Change-Number: 50527 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2021