coreboot-gerrit February 2021

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Change in coreboot[master]: nb/intel/haswell: Drop unused function declaration
by Arthur Heymans (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50540 ) Change subject: nb/intel/haswell: Drop unused function declaration ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica612bcdac373ac013a877bb96b77b2a3f522f7f Gerrit-Change-Number: 50540 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 13:52:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: haswell boards: Correct USB config indentation
by Arthur Heymans (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Tristan Corrick, Angel Pons, Alexander Couzens, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50539 ) Change subject: haswell boards: Correct USB config indentation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35 Gerrit-Change-Number: 50539 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 13:52:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: haswell: Drop `mainboard_fill_pei_data`
by Arthur Heymans (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Tristan Corrick, Angel Pons, Alexander Couzens, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50538 ) Change subject: haswell: Drop `mainboard_fill_pei_data` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e Gerrit-Change-Number: 50538 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 13:51:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncar
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50401 ) Change subject: soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncar ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > will do as soon as the higher priority changes have landed in order to not delay those by merge conf […] just checked and there are no potential merge conflicts with the rest of the recent patches -- To view, visit https://review.coreboot.org/c/coreboot/+/50401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041 Gerrit-Change-Number: 50401 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 13:42:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncar
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Patrick Georgi, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50401 to look at the new patch set (#3). Change subject: soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncar ...................................................................... soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncar The same functionality will eventually be needed on Cezanne. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041 --- M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/picasso/Makefile.inc D src/soc/amd/picasso/memmap.c 3 files changed, 20 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/50401/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041 Gerrit-Change-Number: 50401 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: select ACPI support and make the compiler happy
by Felix Held (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50273 ) Change subject: soc/amd/cezanne: select ACPI support and make the compiler happy ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/50273/comment/8c340400_45a2ef45 PS4, Line 19: select HAVE_ACPI_TABLES > Why not make SOC_AMD_COMMON_BLOCK_ACPI select this? not selecting this in the common acpi code helped a bit to untangle things for cezanne, so i'm not sure if this is a good idea -- To view, visit https://review.coreboot.org/c/coreboot/+/50273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132 Gerrit-Change-Number: 50273 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 13:36:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/slippy: Factor out SPD indexing
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50542 ) Change subject: mb/google/slippy: Factor out SPD indexing ...................................................................... mb/google/slippy: Factor out SPD indexing The code to read the SPD file and index it is not variant-specific. Change-Id: Ifaedc39b683901b60abbb1d984f1d38c1ed364e2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/slippy/romstage.c M src/mainboard/google/slippy/variant.h M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c 6 files changed, 44 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/50542/1 diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index fb32b48..89eaab9 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -1,9 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> +#include <cbfs.h> +#include <console/console.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <string.h> +#include <types.h> + #include "variant.h" void mainboard_config_rcba(void) @@ -46,3 +50,26 @@ spd_map[0] = 0xff; spd_map[2] = 0xff; } + +unsigned int fill_spd_for_index(uint8_t spd[], unsigned int spd_index) +{ + uint8_t *spd_file; + size_t spd_file_len; + + printk(BIOS_DEBUG, "SPD index %d\n", spd_index); + spd_file = cbfs_map("spd.bin", &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + memcpy(spd, spd_file + (spd_index * SPD_LEN), SPD_LEN); + + return spd_index; +} diff --git a/src/mainboard/google/slippy/variant.h b/src/mainboard/google/slippy/variant.h index bfcf855..f1aa6ab 100644 --- a/src/mainboard/google/slippy/variant.h +++ b/src/mainboard/google/slippy/variant.h @@ -3,4 +3,8 @@ #ifndef VARIANT_H #define VARIANT_H +#include <stdint.h> + +unsigned int fill_spd_for_index(uint8_t spd[], unsigned int index); + #endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 8870fae..21a4ec6 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -1,11 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stddef.h> #include <string.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> @@ -15,33 +10,15 @@ void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; - int spd_index = get_gpios(gpio_vector); - char *spd_file; - size_t spd_file_len; - size_t spd_len = sizeof(peid->spd_data[0]); - printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_map("spd.bin", &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * spd_len)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < spd_len) - die("Missing SPD data."); - - memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); + unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector)); /* Index 0-2,6 are 4GB config with both CH0 and CH1 * Index 3-5,7 are 2GB config with CH0 only */ switch (spd_index) { case 0: case 1: case 2: case 6: - memcpy(peid->spd_data[1], - spd_file + (spd_index * spd_len), spd_len); + memcpy(peid->spd_data[1], peid->spd_data[0], SPD_LEN); break; case 3: case 4: case 5: case 7: peid->dimm_channel1_disabled = 3; diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 49961d9..938590b 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -1,10 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> @@ -14,25 +10,8 @@ void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; - int spd_index = get_gpios(gpio_vector); - char *spd_file; - size_t spd_file_len; - size_t spd_len = sizeof(peid->spd_data[0]); - printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_map("spd.bin", &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * spd_len)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < spd_len) - die("Missing SPD data."); - - memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); + unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector)); /* Limiting to a single dimm for 2GB configuration * Identified by bit 3 @@ -40,8 +19,7 @@ if (spd_index & 0x4) peid->dimm_channel1_disabled = 3; else - memcpy(peid->spd_data[1], - spd_file + (spd_index * spd_len), spd_len); + memcpy(peid->spd_data[1], peid->spd_data[0], SPD_LEN); } const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 8a3486a..02b47db 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -2,11 +2,7 @@ #include <stdint.h> #include <string.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/intel/haswell/haswell.h> -#include "ec/google/chromeec/ec.h" -#include <northbridge/intel/haswell/haswell.h> +#include <ec/google/chromeec/ec.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> @@ -17,27 +13,10 @@ void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; - int spd_index = get_gpios(gpio_vector); - char *spd_file; - size_t spd_file_len; - size_t spd_len = sizeof(peid->spd_data[0]); + + unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector)); + uint32_t board_version = PEPPY_BOARD_VERSION_PROTO; - - printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_map("spd.bin", &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < spd_len) - die("Missing SPD data."); - - memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); - google_chromeec_get_board_version(&board_version); switch (board_version) { case PEPPY_BOARD_VERSION_PROTO: @@ -45,8 +24,7 @@ if (spd_index == 0) peid->dimm_channel1_disabled = 3; else - memcpy(peid->spd_data[1], - spd_file + (spd_index * spd_len), spd_len); + memcpy(peid->spd_data[1], peid->spd_data[0], SPD_LEN); break; case PEPPY_BOARD_VERSION_EVT: @@ -56,8 +34,7 @@ if (spd_index > 3) peid->dimm_channel1_disabled = 3; else - memcpy(peid->spd_data[1], - spd_file + (spd_index * spd_len), spd_len); + memcpy(peid->spd_data[1], peid->spd_data[0], SPD_LEN); break; } } diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 9080f46..939d584 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -1,11 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/intel/haswell/haswell.h> -#include "ec/google/chromeec/ec.h" -#include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> @@ -15,33 +10,15 @@ void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; - int spd_index = get_gpios(gpio_vector); - char *spd_file; - size_t spd_file_len; - size_t spd_len = sizeof(peid->spd_data[0]); - printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_map("spd.bin", &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * spd_len)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < spd_len) - die("Missing SPD data."); - - memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); + unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector)); /* Index 0-2, are 4GB config with both CH0 and CH1 * Index 3-5, are 2GB config with CH0 only */ switch (spd_index) { case 0: case 1: case 2: - memcpy(peid->spd_data[1], - spd_file + (spd_index * spd_len), spd_len); + memcpy(peid->spd_data[1], peid->spd_data[0], SPD_LEN); break; case 3: case 4: case 5: peid->dimm_channel1_disabled = 3; -- To view, visit https://review.coreboot.org/c/coreboot/+/50542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifaedc39b683901b60abbb1d984f1d38c1ed364e2 Gerrit-Change-Number: 50542 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/pei_data.h: Define `SPD_LEN`
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50541 ) Change subject: nb/intel/haswell/pei_data.h: Define `SPD_LEN` ...................................................................... nb/intel/haswell/pei_data.h: Define `SPD_LEN` Change-Id: I34561372bcdd00b1b3e4dcd6be89fa47d2af9b42 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/pei_data.h 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/50541/1 diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 6bdfde4..4f2f80d 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -8,6 +8,8 @@ typedef void (*tx_byte_func)(unsigned char byte); #define PEI_VERSION 15 +#define SPD_LEN 256 + #define MAX_USB2_PORTS 16 #define MAX_USB3_PORTS 16 #define USB_OC_PIN_SKIP 8 @@ -82,7 +84,7 @@ int usb_xhci_on_resume; struct usb2_port_setting usb2_ports[MAX_USB2_PORTS]; struct usb3_port_setting usb3_ports[MAX_USB3_PORTS]; - uint8_t spd_data[4][256]; + uint8_t spd_data[4][SPD_LEN]; tx_byte_func tx_byte; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/50541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34561372bcdd00b1b3e4dcd6be89fa47d2af9b42 Gerrit-Change-Number: 50541 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: nb/intel/haswell: Drop unused function declaration
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50540 ) Change subject: nb/intel/haswell: Drop unused function declaration ...................................................................... nb/intel/haswell: Drop unused function declaration Change-Id: Ica612bcdac373ac013a877bb96b77b2a3f522f7f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/raminit.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/50540/1 diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index ee0af77..6efea3e 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -18,7 +18,7 @@ void sdram_initialize(struct pei_data *pei_data); void setup_sdram_meminfo(struct pei_data *pei_data); -int fixup_haswell_errata(void); + /* save_mrc_data() must be called after cbmem has been initialized. */ void save_mrc_data(struct pei_data *pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/50540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica612bcdac373ac013a877bb96b77b2a3f522f7f Gerrit-Change-Number: 50540 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: haswell boards: Correct USB config indentation
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Tristan Corrick, Alexander Couzens, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50539 ) Change subject: haswell boards: Correct USB config indentation ...................................................................... haswell boards: Correct USB config indentation Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/hp/folio_9480m/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/msi/h81m-p33/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c 12 files changed, 314 insertions(+), 314 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/50539/1 diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 16f3d0a..1c17fcb 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -25,29 +25,29 @@ spd_map[3] = 0xa6; } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, - { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, - { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - { 1, 0 }, - { 1, 0 }, - { 1, 1 }, - { 1, 1 }, - { 1, 2 }, - { 1, 2 }, - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index b8ecd43..16b1500 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -23,30 +23,30 @@ spd_map[2] = 0xa4; } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - /* Enable, OCn# */ - { 1, 0 }, - { 1, 0 }, - { 0, USB_OC_PIN_SKIP }, - { 0, USB_OC_PIN_SKIP }, - { 0, USB_OC_PIN_SKIP }, - { 0, USB_OC_PIN_SKIP }, - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, + { 1, 0 }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, +}; diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index f009f5a..dda2edc 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -46,30 +46,30 @@ spd_map[2] = 0xa4; } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0064, 1, 0, /* P0: VP8 */ - USB_PORT_MINI_PCIE }, - { 0x0040, 1, 0, /* P1: Port A, CN22 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 1, /* P2: Port B, CN23 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 2, /* P4: Port C, CN25 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 2, /* P5: Port D, CN25 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ - USB_PORT_INTERNAL }, - { 0x0000, 0, 0, /* P7: N/C */ - USB_PORT_SKIP }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0064, 1, 0, /* P0: VP8 */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 0, /* P1: Port A, CN22 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 1, /* P2: Port B, CN23 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 2, /* P4: Port C, CN25 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 2, /* P5: Port D, CN25 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ + USB_PORT_INTERNAL }, + { 0x0000, 0, 0, /* P7: N/C */ + USB_PORT_SKIP }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; CN22 */ - { 1, 1 }, /* P2; CN23 */ - { 1, 2 }, /* P3; CN25 */ - { 1, 2 }, /* P4; CN25 */ - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; CN22 */ + { 1, 1 }, /* P2; CN23 */ + { 1, 2 }, /* P3; CN25 */ + { 1, 2 }, /* P4; CN25 */ +}; diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index de0ac76..8870fae 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -48,30 +48,30 @@ } } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0064, 1, 0, /* P0: Port A, CN8 */ - USB_PORT_BACK_PANEL }, - { 0x0052, 1, 0, /* P1: Port B, CN9 */ - USB_PORT_BACK_PANEL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ - USB_PORT_INTERNAL }, - { 0x0123, 1, 3, /* P7: USB2 Port */ - USB_PORT_INTERNAL }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0064, 1, 0, /* P0: Port A, CN8 */ + USB_PORT_BACK_PANEL }, + { 0x0052, 1, 0, /* P1: Port B, CN9 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_INTERNAL }, + { 0x0123, 1, 3, /* P7: USB2 Port */ + USB_PORT_INTERNAL }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN8 */ - { 1, 0 }, /* P2; Port B, CN9 */ - { 0, USB_OC_PIN_SKIP }, /* P3; */ - { 0, USB_OC_PIN_SKIP }, /* P4; */ - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN8 */ + { 1, 0 }, /* P2; Port B, CN9 */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ +}; diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index daf0c16..49961d9 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -44,30 +44,30 @@ spd_file + (spd_index * spd_len), spd_len); } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, /* P0: Port A, CN10 */ - USB_PORT_BACK_PANEL }, - { 0x0040, 1, 2, /* P1: Port B, CN11 */ - USB_PORT_BACK_PANEL }, - { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ - USB_PORT_MINI_PCIE }, - { 0x0080, 1, USB_OC_PIN_SKIP, /* P4: SD Card */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: LTE */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SIM CARD */ - USB_PORT_FLEX }, - { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ - USB_PORT_SKIP }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, /* P1: Port B, CN11 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P4: SD Card */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: LTE */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SIM CARD */ + USB_PORT_FLEX }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN10 */ - { 1, 2 }, /* P2; Port B, CN11 */ - { 0, USB_OC_PIN_SKIP }, /* P3; */ - { 0, USB_OC_PIN_SKIP }, /* P4; */ - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN10 */ + { 1, 2 }, /* P2; Port B, CN11 */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ +}; diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 535c07b..8a3486a 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -62,30 +62,30 @@ } } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ - USB_PORT_MINI_PCIE }, - { 0x0040, 1, 0, /* P1: Port A, CN10 */ - USB_PORT_BACK_PANEL }, - { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ - USB_PORT_MINI_PCIE }, - { 0x0040, 1, 2, /* P4: Port B, CN6 */ - USB_PORT_BACK_PANEL }, - { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ - USB_PORT_SKIP }, - { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ - USB_PORT_FLEX }, - { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ - USB_PORT_SKIP }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 0, /* P1: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 2, /* P4: Port B, CN6 */ + USB_PORT_BACK_PANEL }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ + USB_PORT_SKIP }, + { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_FLEX }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN6 */ - { 0, USB_OC_PIN_SKIP }, /* P2; */ - { 0, USB_OC_PIN_SKIP }, /* P3; */ - { 0, USB_OC_PIN_SKIP }, /* P4; */ - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN6 */ + { 0, USB_OC_PIN_SKIP }, /* P2; */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ +}; diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 40ff9c2..9080f46 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -48,30 +48,30 @@ } } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, /* P0: Port A, CN10 */ - USB_PORT_BACK_PANEL }, - { 0x0040, 1, 2, /* P1: Port B, CN11 */ - USB_PORT_BACK_PANEL }, - { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ - USB_PORT_MINI_PCIE }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ - USB_PORT_INTERNAL }, - { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */ - USB_PORT_SKIP }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ - USB_PORT_INTERNAL }, - { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ - USB_PORT_SKIP }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, /* P1: Port B, CN11 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ + USB_PORT_INTERNAL }, + { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */ + USB_PORT_SKIP }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_INTERNAL }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN10 */ - { 1, 2 }, /* P2; Port B, CN11 */ - { 0, USB_OC_PIN_SKIP }, /* P3; */ - { 0, USB_OC_PIN_SKIP }, /* P4; */ - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN10 */ + { 1, 2 }, /* P2; Port B, CN11 */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ +}; diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c index 0c4308b..496005d 100644 --- a/src/mainboard/hp/folio_9480m/romstage.c +++ b/src/mainboard/hp/folio_9480m/romstage.c @@ -23,21 +23,21 @@ spd_map[2] = 0xa4; } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */ - { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */ - { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* right */ - { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WLAN */ - { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* SmartCard */ - { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WWAN */ - { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */ - { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* right */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WLAN */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* SmartCard */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WWAN */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - { 1, USB_OC_PIN_SKIP }, /* dock */ - { 1, USB_OC_PIN_SKIP }, /* left */ - { 1, USB_OC_PIN_SKIP }, /* right */ - { 0, USB_OC_PIN_SKIP }, - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, USB_OC_PIN_SKIP }, /* dock */ + { 1, USB_OC_PIN_SKIP }, /* left */ + { 1, USB_OC_PIN_SKIP }, /* right */ + { 0, USB_OC_PIN_SKIP }, +}; diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 9c4c9b7..dc1f50f 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -49,44 +49,44 @@ spd_map[3] = 0xa6; } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ - USB_PORT_BACK_PANEL }, - { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */ - USB_PORT_BACK_PANEL }, - { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */ - USB_PORT_FLEX }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */ - USB_PORT_DOCK }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */ - USB_PORT_MINI_PCIE }, - { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */ - USB_PORT_FLEX }, - { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */ - USB_PORT_FRONT_PANEL }, - { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */ - USB_PORT_FRONT_PANEL }, - { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */ - USB_PORT_FRONT_PANEL }, - { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */ - USB_PORT_FRONT_PANEL }, - { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */ - USB_PORT_FRONT_PANEL }, - { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */ - USB_PORT_FRONT_PANEL }, - { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */ - USB_PORT_FRONT_PANEL }, - { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */ - USB_PORT_FRONT_PANEL }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */ + USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */ + USB_PORT_DOCK }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */ + USB_PORT_FLEX }, + { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */ + USB_PORT_FRONT_PANEL }, + { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */ + USB_PORT_FRONT_PANEL }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; */ - { 1, 0 }, /* P2; */ - { 1, 0 }, /* P3; */ - { 1, 0 }, /* P4; */ - { 1, 0 }, /* P6; */ - { 1, 0 }, /* P6; */ - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; */ + { 1, 0 }, /* P2; */ + { 1, 0 }, /* P3; */ + { 1, 0 }, /* P4; */ + { 1, 0 }, /* P6; */ + { 1, 0 }, /* P6; */ +}; diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index eaee734..7aca7c5 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -46,29 +46,29 @@ spd_map[2] = 0xa2; } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ - { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* USB2 charge */ - { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, - { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, - { 0x0080, 1, 2, USB_PORT_BACK_PANEL }, /* USB2 */ - { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* WWAN */ - { 0x0040, 1, 5, USB_PORT_INTERNAL }, /* WLAN */ - { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, /* webcam */ - { 0x0080, 1, 6, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* USB2 charge */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, + { 0x0080, 1, 2, USB_PORT_BACK_PANEL }, /* USB2 */ + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* WWAN */ + { 0x0040, 1, 5, USB_PORT_INTERNAL }, /* WLAN */ + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, /* webcam */ + { 0x0080, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - { 1, 0 }, - { 1, 0 }, - { 1, USB_OC_PIN_SKIP }, - { 1, USB_OC_PIN_SKIP }, - { 1, 1 }, - { 1, 1 }, /* WWAN */ - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 1 }, /* WWAN */ +}; diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c index 56c77cd..9bcb400 100644 --- a/src/mainboard/msi/h81m-p33/romstage.c +++ b/src/mainboard/msi/h81m-p33/romstage.c @@ -23,29 +23,29 @@ spd_map[2] = 0xa4; } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, - { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, - { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - { 1, 0 }, - { 1, 0 }, - { 1, 1 }, - { 1, 1 }, - { 1, 2 }, - { 1, 2 }, - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index a2798d9..36f79a3 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -25,30 +25,30 @@ spd_map[3] = 0xa6; } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, USB_PORT_INTERNAL }, - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, - { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, - { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, - { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_INTERNAL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - /* Enable, OCn# */ - { 1, 1 }, - { 1, 1 }, - { 0, USB_OC_PIN_SKIP }, - { 0, USB_OC_PIN_SKIP }, - { 1, 3 }, - { 1, 3 }, - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 1 }, + { 1, 1 }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, + { 1, 3 }, + { 1, 3 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/50539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35 Gerrit-Change-Number: 50539 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021