coreboot-gerrit February 2021

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Change in coreboot[master]: cpu/intel/microcode: Fix typo in function parameter
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50441 ) Change subject: cpu/intel/microcode: Fix typo in function parameter ...................................................................... cpu/intel/microcode: Fix typo in function parameter Change-Id: I9b03105a6808a67c2101917e1822729407271627 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50441 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/microcode/microcode.c M src/include/cpu/intel/microcode.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 8673990..2c8a212 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -187,7 +187,7 @@ } #if ENV_RAMSTAGE -__weak int soc_skip_ucode_update(u32 currrent_patch_id, +__weak int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) { return 0; diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 7fd6eac..a0ab7fd 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -17,7 +17,7 @@ /* SoC specific check to determine if microcode update is really * required, will skip microcode update if true. */ -int soc_skip_ucode_update(u32 currrent_patch_id, u32 new_patch_id); +int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id); /* return the version of the currently running microcode */ uint32_t get_current_microcode_rev(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/50441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b03105a6808a67c2101917e1822729407271627 Gerrit-Change-Number: 50441 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/{haswell,sandybridge}/*/mchbar.h: Fix typo in comment
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50440 ) Change subject: nb/intel/{haswell,sandybridge}/*/mchbar.h: Fix typo in comment ...................................................................... nb/intel/{haswell,sandybridge}/*/mchbar.h: Fix typo in comment Change-Id: Ie41433ed8fcadec25007c436ec12163d729a2afe Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50440 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/registers/mchbar.h M src/northbridge/intel/sandybridge/registers/mchbar.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index a61036a..2dfad62 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -13,7 +13,7 @@ #define MC_INIT_STATE_G 0x5030 #define MRC_REVISION 0x5034 /* MRC Revision */ -#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ +#define MC_LOCK 0x50fc /* Memory Controller Lock register */ #define GFXVTBAR 0x5400 /* Base address for IGD */ #define EDRAMBAR 0x5408 /* Base address for eDRAM */ diff --git a/src/northbridge/intel/sandybridge/registers/mchbar.h b/src/northbridge/intel/sandybridge/registers/mchbar.h index 2fe6b24..d3df3c0 100644 --- a/src/northbridge/intel/sandybridge/registers/mchbar.h +++ b/src/northbridge/intel/sandybridge/registers/mchbar.h @@ -483,7 +483,7 @@ #define ECC_INJ_ADDR_COMPARE 0x5090 /* Address compare for ECC error inject */ #define ECC_INJ_ADDR_MASK 0x5094 /* Address mask for ECC error inject */ -#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ +#define MC_LOCK 0x50fc /* Memory Controller Lock register */ #define GFXVTBAR 0x5400 /* Base address for IGD */ #define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie41433ed8fcadec25007c436ec12163d729a2afe Gerrit-Change-Number: 50440 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/amd/agesa/hudson/amd_pci_int_defs.h: Fix comments
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50425 ) Change subject: sb/amd/agesa/hudson/amd_pci_int_defs.h: Fix comments ...................................................................... sb/amd/agesa/hudson/amd_pci_int_defs.h: Fix comments Change-Id: Iff701d8e6d672b3ca97d9d6361ba48736c06c6c1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50425 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index 16904f1..20c15f0 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -28,9 +28,9 @@ #define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ #define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ #define PIRQ_ASF 0x12 /* ASF */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff701d8e6d672b3ca97d9d6361ba48736c06c6c1 Gerrit-Change-Number: 50425 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/amd/agesa/hudson: Drop setting `ACPI_FADT_RESET_REGISTER`
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50424 ) Change subject: sb/amd/agesa/hudson: Drop setting `ACPI_FADT_RESET_REGISTER` ...................................................................... sb/amd/agesa/hudson: Drop setting `ACPI_FADT_RESET_REGISTER` It is already set in `src/arch/x86/acpi.c` function `arch_fill_fadt`. Change-Id: Ica7e112ca253d1332ed2ea414948c8f1970d0a69 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50424 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/southbridge/amd/agesa/hudson/fadt.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index ee696ed..ba9e47d 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -58,7 +58,6 @@ ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_32BIT_TIMER | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_PCI_EXPRESS_WAKE | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_S4_RTC_VALID | -- To view, visit https://review.coreboot.org/c/coreboot/+/50424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica7e112ca253d1332ed2ea414948c8f1970d0a69 Gerrit-Change-Number: 50424 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50423 ) Change subject: sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros ...................................................................... sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros Tested with BUILD_TIMELESS=1, Lenovo G505s remains identical. Change-Id: I759bdef44f7ca0f35350901998f6820820005b38 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50423 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/southbridge/amd/agesa/hudson/sm.c 1 file changed, 0 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index a6b1464..6f9e03c 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -14,41 +14,6 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#define BIT0 (1 << 0) -#define BIT1 (1 << 1) -#define BIT2 (1 << 2) -#define BIT3 (1 << 3) -#define BIT4 (1 << 4) -#define BIT5 (1 << 5) -#define BIT6 (1 << 6) -#define BIT7 (1 << 7) - -#define BIT8 (1 << 8) -#define BIT9 (1 << 9) -#define BIT10 (1 << 10) -#define BIT11 (1 << 11) -#define BIT12 (1 << 12) -#define BIT13 (1 << 13) -#define BIT14 (1 << 14) -#define BIT15 (1 << 15) - -#define BIT16 (1 << 16) -#define BIT17 (1 << 17) -#define BIT18 (1 << 18) -#define BIT19 (1 << 19) -#define BIT20 (1 << 20) -#define BIT21 (1 << 21) -#define BIT22 (1 << 22) -#define BIT23 (1 << 23) -#define BIT24 (1 << 24) -#define BIT25 (1 << 25) -#define BIT26 (1 << 26) -#define BIT27 (1 << 27) -#define BIT28 (1 << 28) -#define BIT29 (1 << 29) -#define BIT30 (1 << 30) -#define BIT31 (1 << 31) - /* * HUDSON enables all USB controllers by default in SMBUS Control. * HUDSON enables SATA by default in SMBUS Control. -- To view, visit https://review.coreboot.org/c/coreboot/+/50423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I759bdef44f7ca0f35350901998f6820820005b38 Gerrit-Change-Number: 50423 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Michał Żygowski. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50423 ) Change subject: sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I759bdef44f7ca0f35350901998f6820820005b38 Gerrit-Change-Number: 50423 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 11 Feb 2021 10:18:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/amd/pi/hudson/pci.c: Remove empty init operation
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50422 ) Change subject: sb/amd/pi/hudson/pci.c: Remove empty init operation ...................................................................... sb/amd/pi/hudson/pci.c: Remove empty init operation Change-Id: I5620867b3044936be8ad1bf95255be5a3565bb51 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50422 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/southbridge/amd/pi/hudson/pci.c 1 file changed, 0 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index 3dd0368..5e828f7 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -7,10 +7,6 @@ #include <southbridge/amd/common/amd_pci_util.h> #include <bootstate.h> -static void pci_init(struct device *dev) -{ -} - /* * Update the PCI devices with a valid IRQ number * that is set in the mainboard PCI_IRQ structures. @@ -38,7 +34,6 @@ .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, .ops_pci = &lops_pci, -- To view, visit https://review.coreboot.org/c/coreboot/+/50422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5620867b3044936be8ad1bf95255be5a3565bb51 Gerrit-Change-Number: 50422 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/amd/pi/hudson/imc.c: Remove duplicated comment
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50421 ) Change subject: sb/amd/pi/hudson/imc.c: Remove duplicated comment ...................................................................... sb/amd/pi/hudson/imc.c: Remove duplicated comment Change-Id: Ie2de3948a78352bbb68c9215222b8489cacb91ce Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50421 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/southbridge/amd/pi/hudson/imc.c 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c index fd9a372..81b0e26 100644 --- a/src/southbridge/amd/pi/hudson/imc.c +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -19,8 +19,6 @@ u8 reg8; /* Init Power Management Block 2 (PM2) Registers. * Check BKDG for AMD Family 16h for details. */ - /* Init Power Management Block 2 (PM2) Registers. - * Check BKDG for AMD Family 16h for details. */ pm2_write8(0, 0x06); pm2_write8(1, 0x06); pm2_write8(2, 0xf7); -- To view, visit https://review.coreboot.org/c/coreboot/+/50421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2de3948a78352bbb68c9215222b8489cacb91ce Gerrit-Change-Number: 50421 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork: modify ELAN TP i2c IRQ to LEVEL active for dirinboz
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50420 ) Change subject: mb/google/zork: modify ELAN TP i2c IRQ to LEVEL active for dirinboz ...................................................................... mb/google/zork: modify ELAN TP i2c IRQ to LEVEL active for dirinboz configure IRQs as level triggered to prevent TP lost. BUG=None BRANCH=zork TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on, suspend DUT to check TP is functional Change-Id: I81ffa889fbdfb01bf3057a8258fb4dd4ad7e88d5 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50420 Reviewed-by: Sam McNally <sammc(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 283b1fc..43f4ff7 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -111,7 +111,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "wake" = "GEVENT_22" register "probed" = "1" device i2c 15 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/50420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ffa889fbdfb01bf3057a8258fb4dd4ad7e88d5 Gerrit-Change-Number: 50420 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "mb/intel/shadowmountain: Add the ASL code"
by Subrata Banik (Code Review) 11 Feb '21

11 Feb '21

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50055 ) Change subject: Revert "mb/intel/shadowmountain: Add the ASL code" ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Landing early with 3x +2 to unbreak master. Thanks Angel -- To view, visit https://review.coreboot.org/c/coreboot/+/50055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fa5e8cc2ad485bf82bfbda151bc46d26faef7ab Gerrit-Change-Number: 50055 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 11 Feb 2021 10:16:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2021