coreboot-gerrit February 2021

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Change in coreboot[master]: [RFC] drivers/spi: Stop using a variable-length array (alt)
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50519 ) Change subject: [RFC] drivers/spi: Stop using a variable-length array (alt) ...................................................................... [RFC] drivers/spi: Stop using a variable-length array (alt) Change-Id: Ic432a75fce24b94fb4f3b74fa52ce925e12219a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/spi/spi_flash.c M src/drivers/spi/spi_flash_internal.h M src/drivers/spi/sst.c M src/drivers/spi/winbond.c 4 files changed, 37 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/50519/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index b674749..bd70b93 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -88,21 +88,10 @@ return ret; } -/* TODO: This code is quite possibly broken and overflowing stacks. Fix ASAP! */ -#pragma GCC diagnostic push -#if defined(__GNUC__) && !defined(__clang__) -#pragma GCC diagnostic ignored "-Wstack-usage=" -#endif -#pragma GCC diagnostic ignored "-Wvla" -int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, - size_t cmd_len, const void *data, size_t data_len) +int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *buff, + size_t cmd_len, size_t data_len) { - int ret; - u8 buff[cmd_len + data_len]; - memcpy(buff, cmd, cmd_len); - memcpy(buff + cmd_len, data, data_len); - - ret = do_spi_flash_cmd(spi, buff, cmd_len + data_len, NULL, 0); + int ret = do_spi_flash_cmd(spi, buff, cmd_len + data_len, NULL, 0); if (ret) { printk(BIOS_WARNING, "SF: Failed to send write command (%zu bytes): %d\n", data_len, ret); @@ -110,7 +99,6 @@ return ret; } -#pragma GCC diagnostic pop /* Perform the read operation honoring spi controller fifo size, reissuing * the read command until the full request completed. */ @@ -221,7 +209,7 @@ if (ret) goto out; - ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), NULL, 0); + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), 0); if (ret) goto out; @@ -242,6 +230,8 @@ return spi_flash_cmd(&flash->spi, flash->status_cmd, reg, sizeof(*reg)); } +#define MAX_FLASH_CMD_DATA_SIZE 256 + int spi_flash_cmd_write_page_program(const struct spi_flash *flash, u32 offset, size_t len, const void *buf) { @@ -250,20 +240,22 @@ size_t chunk_len; size_t actual; int ret = 0; - u8 cmd[4]; + u8 cmd_data[4 + MAX_FLASH_CMD_DATA_SIZE]; page_size = flash->page_size; - cmd[0] = flash->pp_cmd; + cmd_data[0] = flash->pp_cmd; for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; chunk_len = MIN(len - actual, page_size - byte_addr); - chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); + chunk_len = spi_crop_chunk(&flash->spi, 4, chunk_len); + chunk_len = MIN(chunk_len, MAX_FLASH_CMD_DATA_SIZE); - spi_flash_addr(offset, cmd); + spi_flash_addr(offset, cmd_data); if (CONFIG(DEBUG_SPI_FLASH)) { printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", - buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], + buf + actual, + cmd_data[0], cmd_data[1], cmd_data[2], cmd_data[3], chunk_len); } @@ -273,8 +265,8 @@ goto out; } - ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), - buf + actual, chunk_len); + memcpy(&cmd_data[4], buf + actual, chunk_len); + ret = spi_flash_cmd_write(&flash->spi, cmd_data, 4, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: Page Program failed\n"); goto out; diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index b4d39b3..fdf8d77 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -31,8 +31,8 @@ * Send a multi-byte command to the device followed by (optional) * data. Used for programming the flash array, etc. */ -int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, - size_t cmd_len, const void *data, size_t data_len); +int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *buff, + size_t cmd_len, size_t data_len); /* Send a command to the device and wait for some bit to clear itself. */ int spi_flash_cmd_poll_bit(const struct spi_flash *flash, unsigned long timeout, diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 887380f..a514bfa 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -115,26 +115,27 @@ } static int -sst_byte_write(const struct spi_flash *flash, u32 offset, const void *buf) +sst_byte_write(const struct spi_flash *flash, u32 offset, const u8 *buf) { int ret; - u8 cmd[4] = { + u8 cmd_data[4 + 1] = { CMD_SST_BP, offset >> 16, offset >> 8, offset, + *buf, }; #if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "BP[%02x]: %p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(&flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); + spi_w8r8(&flash->spi, CMD_SST_RDSR), buf, cmd_data[0], offset); #endif ret = sst_enable_writing(flash); if (ret) return ret; - ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf, 1); + ret = spi_flash_cmd_write(&flash->spi, cmd_data, 4, 1); if (ret) return ret; @@ -146,7 +147,7 @@ { size_t actual, cmd_len; int ret = 0; - u8 cmd[4]; + u8 cmd_data[4 + 2]; /* If the data is not word aligned, write out leading single byte */ actual = offset % 2; @@ -162,20 +163,21 @@ goto done; cmd_len = 4; - cmd[0] = CMD_SST_AAI_WP; - cmd[1] = offset >> 16; - cmd[2] = offset >> 8; - cmd[3] = offset; + cmd_data[0] = CMD_SST_AAI_WP; + cmd_data[1] = offset >> 16; + cmd_data[2] = offset >> 8; + cmd_data[3] = offset; for (; actual < len - 1; actual += 2) { #if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "WP[%02x]: %p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(&flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], + spi_w8r8(&flash->spi, CMD_SST_RDSR), buf + actual, cmd_data[0], offset); #endif - ret = spi_flash_cmd_write(&flash->spi, cmd, cmd_len, - buf + actual, 2); + cmd_data[4] = *(u8 *)(buf + actual + 0); + cmd_data[5] = *(u8 *)(buf + actual + 1); + ret = spi_flash_cmd_write(&flash->spi, cmd_data, cmd_len, 2); if (ret) { printk(BIOS_WARNING, "SF: SST word program failed\n"); break; @@ -209,15 +211,16 @@ static int sst_unlock(const struct spi_flash *flash) { int ret; - u8 cmd, status; + u8 cmd_data[1 + 1] = { + CMD_SST_WRSR, + 0, + }; ret = sst_enable_writing_status(flash); if (ret) return ret; - cmd = CMD_SST_WRSR; - status = 0; - ret = spi_flash_cmd_write(&flash->spi, &cmd, 1, &status, 1); + ret = spi_flash_cmd_write(&flash->spi, cmd_data, 1, 1); if (ret) printk(BIOS_WARNING, "SF: Unable to set status byte\n"); diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index e4151de..d4b79bc 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -355,8 +355,7 @@ cmdbuf.cmd = CMD_W25_WRSR; /* Legacy method of writing status register 1 & 2 */ - ret = spi_flash_cmd_write(&flash->spi, (u8 *)&cmdbuf, sizeof(cmdbuf), - NULL, 0); + ret = spi_flash_cmd_write(&flash->spi, (u8 *)&cmdbuf, sizeof(cmdbuf), 0); if (ret) return ret; -- To view, visit https://review.coreboot.org/c/coreboot/+/50519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic432a75fce24b94fb4f3b74fa52ce925e12219a4 Gerrit-Change-Number: 50519 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "abuild: Allow disabling mainboards"
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Martin Roth, Julius Werner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50518 ) Change subject: Revert "abuild: Allow disabling mainboards" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e2f2e1a5d4617baa49cbcb1a640a1ea270007ef Gerrit-Change-Number: 50518 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 10:48:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/abuild: Ensure that non-Chrome OS builds are non-Chrome OS
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Martin Roth, Julius Werner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50494 ) Change subject: util/abuild: Ensure that non-Chrome OS builds are non-Chrome OS ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb6bcbf3e9ca8cd4ced85c7c9ffaa39505f5a9b7 Gerrit-Change-Number: 50494 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 10:47:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "abuild: Allow disabling mainboards"
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Martin Roth, Julius Werner. Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50518 ) Change subject: Revert "abuild: Allow disabling mainboards" ...................................................................... Revert "abuild: Allow disabling mainboards" This reverts commit 3ac3c4ebac8 ("abuild: Allow disabling mainboards"). This mechanism helped getting Chrome OS' coreboot divergence sorted out in the 2015/2016 timeframe but hasn't been used by anybody since then. Let's not encourage people to push non-working builds without good reason and discussion (the result of which could be that we re-introduce this mechanism). Change-Id: I8e2f2e1a5d4617baa49cbcb1a640a1ea270007ef Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/abuild/abuild 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/50518/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 408de12..63aee2b 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -421,12 +421,6 @@ return fi - if [ -f "src/mainboard/${board_srcdir}/abuild.disabled" ]; then - echo "${BUILD_NAME} disabled:" - cat "src/mainboard/${board_srcdir}/abuild.disabled" - return - fi - if [ "$quiet" == "false" ]; then echo "Building $BUILD_NAME"; fi mkdir -p "$TARGET/${BUILD_NAME}" "$TARGET/abuild" ABSPATH="$(cd "$TARGET/abuild" && pwd)" -- To view, visit https://review.coreboot.org/c/coreboot/+/50518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e2f2e1a5d4617baa49cbcb1a640a1ea270007ef Gerrit-Change-Number: 50518 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/abuild: Ensure that non-Chrome OS builds are non-Chrome OS
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Martin Roth, Julius Werner. Hello build bot (Jenkins), Martin Roth, Angel Pons, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50494 to look at the new patch set (#2). Change subject: util/abuild: Ensure that non-Chrome OS builds are non-Chrome OS ...................................................................... util/abuild: Ensure that non-Chrome OS builds are non-Chrome OS Sometimes boards enable it by default, making the Kconfig option impossible to disable without messing with the Kconfig files. This shouldn't happen, so report on such occurrences early. TEST=Tried building GOOGLE_KOHAKU through abuild with -x, without -x and both cases after having added a "select CHROMEOS" for testing and it failed in the "without -x with select" scenario while properly configuring and passing all other builds. Change-Id: Ieb6bcbf3e9ca8cd4ced85c7c9ffaa39505f5a9b7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/abuild/abuild 1 file changed, 24 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50494/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb6bcbf3e9ca8cd4ced85c7c9ffaa39505f5a9b7 Gerrit-Change-Number: 50494 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/lynxpoint: Clean up lp_gpio.h
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Nico Huber, Arthur Heymans, Patrick Rudolph. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50065 ) Change subject: sb/intel/lynxpoint: Clean up lp_gpio.h ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I436d7fdabf8d574e5dd2787fb6097f384cc8e453 Gerrit-Change-Number: 50065 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 10:29:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/broadwell/pch: Rename GPIO identifiers
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Attention is currently required from: Nico Huber, Arthur Heymans, Patrick Rudolph. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50064 ) Change subject: soc/intel/broadwell/pch: Rename GPIO identifiers ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11ea27b00b5820eb5553712e0420836470ec0d27 Gerrit-Change-Number: 50064 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Feb 2021 10:29:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src: Remove unused <cpu/intel/model_206ax/model_206ax.h>
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50170 ) Change subject: src: Remove unused <cpu/intel/model_206ax/model_206ax.h> ...................................................................... src: Remove unused <cpu/intel/model_206ax/model_206ax.h> Change-Id: I67862a6a5110e2cab4f77388caa702494e4d71c9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50170 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/stout/smihandler.c M src/mainboard/intel/emeraldlake2/smihandler.c M src/mainboard/samsung/lumpy/smihandler.c M src/mainboard/samsung/stumpy/smihandler.c M src/northbridge/intel/sandybridge/raminit_common.h 8 files changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/butterfly/smihandler.c b/src/mainboard/google/butterfly/smihandler.c index 71e7aad..23bd683 100644 --- a/src/mainboard/google/butterfly/smihandler.c +++ b/src/mainboard/google/butterfly/smihandler.c @@ -6,7 +6,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <cpu/intel/model_206ax/model_206ax.h> /* Include EC functions */ #include <ec/quanta/ene_kb3940q/ec.h> diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index fa9f9f9..719076b 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -8,7 +8,6 @@ #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <cpu/intel/model_206ax/model_206ax.h> #include <elog.h> /* Include EC functions */ diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 451c3a9..05f14af 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -8,7 +8,6 @@ #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <cpu/intel/model_206ax/model_206ax.h> #include <ec/compal/ene932/ec.h> #include "ec.h" diff --git a/src/mainboard/google/stout/smihandler.c b/src/mainboard/google/stout/smihandler.c index 7412294..47cb0eb 100644 --- a/src/mainboard/google/stout/smihandler.c +++ b/src/mainboard/google/stout/smihandler.c @@ -8,7 +8,6 @@ #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <cpu/intel/model_206ax/model_206ax.h> /* Include EC functions */ #include <ec/quanta/it8518/ec.h> diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c index b1676d4..9f9a081 100644 --- a/src/mainboard/intel/emeraldlake2/smihandler.c +++ b/src/mainboard/intel/emeraldlake2/smihandler.c @@ -7,7 +7,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <cpu/intel/model_206ax/model_206ax.h> /* * Change LED_POWER# (SIO GPIO 45) state based on sleep type. diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index 773c344..7f279b2 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -7,7 +7,6 @@ #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <cpu/intel/model_206ax/model_206ax.h> #include <ec/smsc/mec1308/ec.h> #include "ec.h" diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 635cc52..2477a58 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -7,7 +7,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <cpu/intel/model_206ax/model_206ax.h> /* Include for SIO helper functions */ #include <superio/ite/it8772f/it8772f.h> diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 0015a09..c43378d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -3,7 +3,6 @@ #ifndef RAMINIT_COMMON_H #define RAMINIT_COMMON_H -#include <cpu/intel/model_206ax/model_206ax.h> #include <stdint.h> #define BASEFREQ 133 -- To view, visit https://review.coreboot.org/c/coreboot/+/50170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67862a6a5110e2cab4f77388caa702494e4d71c9 Gerrit-Change-Number: 50170 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src: Remove unused <arch/cpu.h>
by Patrick Georgi (Code Review) 11 Feb '21

11 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50172 ) Change subject: src: Remove unused <arch/cpu.h> ...................................................................... src: Remove unused <arch/cpu.h> Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/finalize.c M src/cpu/intel/haswell/romstage.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c M src/northbridge/intel/sandybridge/raminit_common.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 16 files changed, 5 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index 3bf9225..3983876 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <types.h> -#include <arch/cpu.h> #include <cpu/x86/msr.h> + #include "haswell.h" void intel_cpu_haswell_finalize_smm(void) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 3b11e93..c745494 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <console/console.h> #include <cpu/intel/haswell/haswell.h> #include <cpu/x86/msr.h> diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index e1fa968..6910713 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <types.h> -#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> + #include "model_2065x.h" /* MSR Documentation based on diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 2298684..afdb7df 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <types.h> -#include <arch/cpu.h> #include <cpu/x86/msr.h> + #include "model_206ax.h" /* MSR Documentation based on diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 8d6aae9..5a7fa57 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> -#include "board_id.h" #include <baseboard/variants.h> #include <soc/romstage.h> +#include "board_id.h" + static const struct mb_cfg ddr4_mem_config = { .type = MEM_TYPE_DDR4, diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c index e965e6b..eedb408 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <baseboard/variants.h> #include <intelblocks/mp_init.h> diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c index 8e7bb14..cf2c1b9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <baseboard/variants.h> #include <intelblocks/mp_init.h> diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index cef0131..2c16818 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <string.h> -#include <arch/cpu.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <northbridge/intel/sandybridge/chip.h> diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 32f5ea2..6de1cb0 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -6,7 +6,6 @@ * Chapter number: 14 */ -#include <arch/cpu.h> #include <console/console.h> #include <device/pci.h> #include <cpu/x86/lapic.h> diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index f60ebd8..5546f27 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <types.h> #include <string.h> -#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> #include <soc/acpi.h> diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 6a4f773..8b845c0 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <console/console.h> #include <device/pci.h> #include <cpu/x86/lapic.h> diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 984f7f2..6d86b0c 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <console/console.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index dd70c85..6c3365b 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <console/console.h> #include <device/pci.h> #include <cpu/x86/lapic.h> diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index a3790e1..8e54eaa 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <console/console.h> #include <device/pci.h> #include <cpu/x86/lapic.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 6872c12..1647db4 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 974401f..925bddb 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -6,7 +6,6 @@ * Chapter number: 15 */ -#include <arch/cpu.h> #include <console/console.h> #include <device/pci.h> #include <cpu/x86/lapic.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a Gerrit-Change-Number: 50172 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/broadwell: Remove _ADR from SerialIO ACPI devices
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46972 ) Change subject: soc/intel/broadwell: Remove _ADR from SerialIO ACPI devices ...................................................................... soc/intel/broadwell: Remove _ADR from SerialIO ACPI devices SerialIO is in ACPI mode for google/auron and intel/wtm2, and is disabled for google/jecht and purism/librem_bdw. Since Broadwell SerialIO is never used in PCI mode, _ADR can safely be dropped. Change-Id: I9a99b8209b5c139146012aa4a92f563692b62c5e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/46972/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 35b15b4..2bacd2b 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -122,7 +122,6 @@ // Serial IO DMA Controller Name (_HID, "INTL9C60") Name (_UID, 1) - Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -168,7 +167,6 @@ Return ("INT33C2") } Name (_UID, 1) - Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -245,7 +243,6 @@ Return ("INT33C3") } Name (_UID, 1) - Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -322,7 +319,6 @@ Return ("INT33C0") } Name (_UID, 1) - Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -384,7 +380,6 @@ Return ("INT33C1") } Name (_UID, 1) - Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -458,7 +453,6 @@ Return ("INT33C4") } Name (_UID, 1) - Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -532,7 +526,6 @@ Return ("INT33C5") } Name (_UID, 1) - Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -595,7 +588,6 @@ } Name (_CID, "PNP0D40") Name (_UID, 1) - Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () -- To view, visit https://review.coreboot.org/c/coreboot/+/46972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a99b8209b5c139146012aa4a92f563692b62c5e Gerrit-Change-Number: 46972 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021