Attention is currently required from: Christian Walter, Julius Werner, Yu-Ping Wu.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59682 )
Change subject: cbfs: Remove deprecated APIs
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Loading a payload should probably not take over two seconds, unless it is ridiculously huge... how big is the payload you use? And do you happen to know the SPI bus speed for your platform?
>
I do have a linux kernel as a payload which is uncmpressed ~4,5 MB in size. And I have a SPI clock of 50 MHz while usung a standard SPI interface (so no dual or quad mode enabled).
>
> Anyway, it should be pretty simple to figure out if this is it: I've uploaded a test CL CB:59767 which just loads the whole payload into RAM before doing anything else with it. Can you try that out and see what difference it makes for your boot times?
I will have access to the hardware tomorrow and will give this test patch a try.
> (If that's not it, could you try narrowing down a bit further where exactly all this time is spent for you? E.g. just sprinkle some timestamp_add_now(1234) with increasing ID numbers throughout the code to see where the big delay comes from.)
Yes, I can try to narrow it down furter.
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Hello Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59790
to look at the new patch set (#2).
Change subject: mb/google/brya: Fix S0i3 regression
......................................................................
mb/google/brya: Fix S0i3 regression
ACPI PM timer needs to be disabled explicitly in CB to increment S0i3
counter as FSP has no control to do the same since
commit:0e905801f8ff6c10b20625e31d851920b3f4c4f2
BUG=b:206922066
TEST=Boot gimble to OS and verify S0i3 counter incrementing
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1
---
M src/mainboard/google/brya/Kconfig
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/59790/2
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Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59790 )
Change subject: mb/google/brya: Fix S0i3 regression
......................................................................
mb/google/brya: Fix S0i3 regression
ACPI PM timer needs to be disabled explicitly in CB since
FSP has no control since this
commit:0e905801f8ff6c10b20625e31d851920b3f4c4f2 in order to
increment S0i3 counter.
BUG=b:206922066
TEST=Boot gimble to OS and verify S0i3 counter incrementing
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1
---
M src/mainboard/google/brya/Kconfig
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/59790/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a5ca942..f01eac3 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -157,4 +157,7 @@
in variant.h, as well as T1_OFF_MS (time between PERST & RST) and T2_OFF_MS (time
between RST and FCPO).
+config USE_PM_ACPI_TIMER
+ default n
+
endif # BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK
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Attention is currently required from: Tim Wawrzynczak, Christian Walter.
Hello Tim Wawrzynczak, Christian Walter,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59768
to look at the new patch set (#2).
Change subject: drivers/i2c/tpm: Add override function for TPM I2C bus
......................................................................
drivers/i2c/tpm: Add override function for TPM I2C bus
Provide a way to let boards can determine which TPM bus to use
at runtime.
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: I658468ed3880de0a6b947c212fa8737956928c57
---
M src/drivers/i2c/tpm/Kconfig
M src/drivers/i2c/tpm/tis.c
M src/drivers/i2c/tpm/tis_atmel.c
M src/security/tpm/tis.h
4 files changed, 18 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/59768/2
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Change subject: soc/intel/common: Add CPU related APIs
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/c/coreboot/+/59124/comment/1ada59b1_ecb95a03
PS1, Line 301: (uint8_t)
> I will do it separate patch.
Ack
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Change subject: soc/intel/alderlake: Add Kconfig for ADL_N PCH
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59751/comment/d617b27d_9096b99c
PS1, Line 7: Adding
> Add
Done
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Change subject: soc/intel/alderlake: Add Kconfig for ADL_N PCH
......................................................................
soc/intel/alderlake: Add Kconfig for ADL_N PCH
Add SOC_INTEL_ALDERLAKE_PCH_N option in Kconfig
Signed-off-by: Usha P <usha.p(a)intel.com>
Change-Id: I1be10aea36db5a14ca8d7cf5c087163e44554f78
---
M src/soc/intel/alderlake/Kconfig
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Change subject: soc/intel/alderlake: Adding Kconfig for ADL_N PCH
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/59751/comment/9d4c7f9c_1e241f72
PS1, Line 14: Choose this option if you have PCH-N chipset.
> Can’t this be auto-detected at runtime?
This is a config to control the compilation specific to ADL-N. Detecting it in runtime would need to parse through all PCH ID's which won't help us in eliminating the compilation overhead.
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