coreboot-gerrit December 2021

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Change in coreboot[master]: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STOR...
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Anil Kumar K, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59638 ) Change subject: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STORAGE_HOB2 HOB introduced in FSP 2.3 ...................................................................... Patch Set 15: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59638/comment/bd2f483c_7af79790 PS15, Line 7: src/ Please remove. https://review.coreboot.org/c/coreboot/+/59638/comment/72cb19f3_fe68ba77 PS15, Line 7: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STORAGE_HOB2 HOB : introduced in FSP 2.3 The commit message summary should be short and fit in one line [1]. [1]: https://chris.beams.io/posts/git-commit/ -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 15 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 01 Dec 2021 10:00:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS
by Kane Chen (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Kangheui Won, Isaac Lee, Reka Norman, chris wang, Felix Held. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59558 ) Change subject: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/zork/variants/shuboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59558/comment/968f3c79_fdef66f0 PS5, Line 2: fw_config > Hi Kane, I will look into why using probe doesn't work. […] Hi Reka Norman, Thanks for your help, we share original version in b:198689479#comment29. -- To view, visit https://review.coreboot.org/c/coreboot/+/59558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749 Gerrit-Change-Number: 59558 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Randy Wang <ifanw(a)google.com> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Dec 2021 09:59:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Furquan Shaikh, Jianjun Wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 6: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56791/comment/866cf744_0b6e6800 PS6, Line 18: SSD Which one exactly? On what board? Please also paste the new log messages here? File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/41208e41_8d41a78d PS6, Line 106: setctions sections https://review.coreboot.org/c/coreboot/+/56791/comment/f56745e7_02fadc87 PS6, Line 111: mdelay(100); That’s pretty long for coreboot. https://review.coreboot.org/c/coreboot/+/56791/comment/a8fc9f3f_5fa2f87c PS6, Line 122: __func__, val); Error messages should be user understandable. Please elaborate, and also document the effects. https://review.coreboot.org/c/coreboot/+/56791/comment/b1acf4d6_b6960dbf PS6, Line 159: res->cpu_addr | PCIE_ATR_SIZE(fls(res->size))); Should fit in one line. https://review.coreboot.org/c/coreboot/+/56791/comment/4446fb36_a4756a43 PS6, Line 174: static int mtk_pcie_dev_assign_resource(struct device *dev, Please excuse my ignorance, but what is special for assigning resources on MediaTek, that no common functions can be used? https://review.coreboot.org/c/coreboot/+/56791/comment/7fbcf086_37d18ce6 PS6, Line 180: printk(BIOS_INFO, "res->index = %#lx\n", res->index); Looks more like debugging or spew? https://review.coreboot.org/c/coreboot/+/56791/comment/211119b2_fcae5cfd PS6, Line 194: __func__, ctrl->mmio_io_size); Plesae add the values to error message. Also, what is the effect and what can be done about it? https://review.coreboot.org/c/coreboot/+/56791/comment/f6476803_b9379401 PS6, Line 289: printk(BIOS_INFO, "%s: Try to probe PCIe bus\n", __func__); 1. Trying … 2. Some success or failure messages is missing? -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 09:57:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C
by Mark Hsieh (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: YH Lin, Paul Menzel, Tim Wawrzynczak, Marco Chen, Felix Held. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59580 ) Change subject: mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59580/comment/adf3b7fc_264cdc4b PS11, Line 13: BUG=b:207613972 > Above you use a different bug number? Hi Paul, No, I used same issue number, only added "b:" -- To view, visit https://review.coreboot.org/c/coreboot/+/59580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7 Gerrit-Change-Number: 59580 Gerrit-PatchSet: 11 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Dec 2021 09:56:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Configure 9 I/O for ADL-N
by Subrata Banik (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Reka Norman, Paul Menzel, Rizwan Qureshi, Krishna P Bhat D, Usha P, Patrick Rudolph, Kangheui Won. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59752 ) Change subject: soc/intel/alderlake: Configure 9 I/O for ADL-N ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59752/comment/57f8de1c_e4e80fb5 PS2, Line 7: Configure 9 I/O for ADL-N don't able to follow what is `9` here. Looking at code, you are just configuring PCIe RP like RP Number, ClkSrC and ClkReq. Why not specify the same ? File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/59752/comment/ea83a692_92f87b0b PS2, Line 177: default Please take a look into this https://chrome-internal.googlesource.com/chromeos/third_party/intel-fsp/adl… The doc that you have shared here page 32 looks data incomplete if you download 645550 doc chapter 21 tell me there are 12 RPs as below. PCIe* Interface (D28:F0-F7 and D29:F0-F3) Registers Summary https://review.coreboot.org/c/coreboot/+/59752/comment/527154bf_a3ad41b2 PS2, Line 193: default 5 if SOC_INTEL_ALDERLAKE_PCH_N also check this https://chrome-internal.googlesource.com/chromeos/third_party/intel-fsp/adl… https://review.coreboot.org/c/coreboot/+/59752/comment/d7b55b7d_837fd941 PS2, Line 199: default 5 if SOC_INTEL_ALDERLAKE_PCH_N same as above -- To view, visit https://review.coreboot.org/c/coreboot/+/59752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 Gerrit-Change-Number: 59752 Gerrit-PatchSet: 2 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 09:51:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM
by Hung-Te Lin (Code Review) 01 Dec '21

01 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59715 ) Change subject: vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM ...................................................................... vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM Fix the issue that power consumption of single rank DRAM is greater than dual rank DRAM due to incorrect settings of rank1 CKE. Set rank1 CKE to the correct state to fix this issue. BUG=b:196867407 TEST=DUT can boot to OS. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: If336197aea4770dda1332b6e83da8ec9a4f9d77b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59715 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index e7e8f89..e3baf7b 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -1946,6 +1946,11 @@ #endif } + if (p->support_rank_num == RANK_SINGLE){ + CKEFixOnOff(p, RANK_1, CKE_DYNAMIC, TO_ALL_CHANNEL); + mcSHOW_DBG_MSG(("Set RANK1 CKE to DYNAMIC\n")); + } + #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) U32 backup_broadcast; backup_broadcast = GetDramcBroadcast(); 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If336197aea4770dda1332b6e83da8ec9a4f9d77b Gerrit-Change-Number: 59715 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM
by Rex-BC Chen (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Ryan Chuang. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59715 ) Change subject: vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: @hung-te, could we merge this patch? thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/59715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If336197aea4770dda1332b6e83da8ec9a4f9d77b Gerrit-Change-Number: 59715 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 09:46:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Enable PCIe support for mt8195
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Hung-Te Lin, Jianjun Wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56793 ) Change subject: soc/mediatek: Enable PCIe support for mt8195 ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56793/comment/ace3400b_0e27e7dc PS6, Line 10: Tested how? -- To view, visit https://review.coreboot.org/c/coreboot/+/56793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Gerrit-Change-Number: 56793 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 09:37:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add driver to configure PCIe
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Hung-Te Lin, Jianjun Wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56792 ) Change subject: soc/mediatek/mt8195: Add driver to configure PCIe ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/mt8195/pcie.c: https://review.coreboot.org/c/coreboot/+/56792/comment/8946358e_be183dc1 PS6, Line 16: { : .cpu_addr = 0x20000000, : .pci_addr = 0x20000000, : .size = 0x1000000, : .type = IORESOURCE_IO, : }, : { : .cpu_addr = 0x21000000, : .pci_addr = 0x21000000, : .size = 0x3000000, : .type = IORESOURCE_MEM, : }, Sorry, last wish from my side. Where are these values from? Maybe add a comment? -- To view, visit https://review.coreboot.org/c/coreboot/+/56792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Gerrit-Change-Number: 56792 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 09:37:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/tpm: Add override function for TPM I2C bus
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Christian Walter, Angel Pons, EricR Lai. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59768 ) Change subject: drivers/i2c/tpm: Add override function for TPM I2C bus ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59768/comment/8b644005_10f79aea PS4, Line 9: can Remove. Patchset: PS4: I think, we avoid using weak functions. -- To view, visit https://review.coreboot.org/c/coreboot/+/59768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I658468ed3880de0a6b947c212fa8737956928c57 Gerrit-Change-Number: 59768 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 09:35:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021