coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya/var/baseboard/brask: Add power limits functions
by Alan Huang (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Paul Menzel, Nick Vaccaro, Zhuohao Lee, Alan Huang. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58241 to look at the new patch set (#17). Change subject: mb/google/brya/var/baseboard/brask: Add power limits functions ...................................................................... mb/google/brya/var/baseboard/brask: Add power limits functions Copy function variant_update_power_limits from brya to set power limits. Add function variant_update_psys_power_limits and copy the algorithm from puff. Add structure system_power_limits and psys_config to define and configure the psys power limits. BUG=b:193864533 BRANCH=none TEST=Build pass Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 --- M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc A src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h 3 files changed, 187 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/58241/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/58241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Gerrit-Change-Number: 58241 Gerrit-PatchSet: 17 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Update camera NVM parameters
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Selma Bensaid, Bernardo Perez Priego, Andy Yeh, kiran2.kumar(a)intel.com, ShawnX Tu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58374 ) Change subject: mb/google/brya: Update camera NVM parameters ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58374/comment/10c12b0c_aa3778b7 PS5, Line 9: Change HID name from INT3499 to PRP0001 along with size and : address width. > Refer to eeprom discussion thread (https://partnerissuetracker.corp.google. […] (I am denied access to that URL.) Please amend the commit message with that information. Also mention the size value decrease and width change. https://review.coreboot.org/c/coreboot/+/58374/comment/a7e161c6_dd2b4bc4 PS5, Line 13: Test=Boot board, camera nvm parameters should be as expected. > Correct the commands to dump the nvm data on brya device. […] Please amend the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/58374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 Gerrit-Change-Number: 58374 Gerrit-PatchSet: 5 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kiran2.kumar(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Attention: kiran2.kumar(a)intel.com Gerrit-Attention: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 10:24:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser
by Jakub Czapiga (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Paul Menzel. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59491 ) Change subject: libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59491/comment/c5b9064a_2704d7e3 PS2, Line 9: many info > much information? Done https://review.coreboot.org/c/coreboot/+/59491/comment/7a20bbb7_b93150a4 PS2, Line 12: Moreover, the MRCDATA (previously MRC_CACHE) should now work on x86. > 1. Please add a blank line above to separate paragraphs visually. […] Ad 1.: Done Ad 2.: I extended the explaination. The corebot tables entry with CB_TAG_MRC_CACHE was is not created anymore. It was replaced by CBMEM IMD entry with id: CBMEM_ID_MRCDATA. Patchset: PS2: > Some minor nits. Thanks :) -- To view, visit https://review.coreboot.org/c/coreboot/+/59491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321 Gerrit-Change-Number: 59491 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 01 Dec 2021 10:24:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser
by Jakub Czapiga (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Jakub Czapiga. Hello build bot (Jenkins), Paul Menzel, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59491 to look at the new patch set (#3). Change subject: libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser ...................................................................... libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser coreboot stores much information in the CBMEM IMD. Until now it was ignored. This patch makes use of these coreboot tables entries. It also removes get_cbmem_addr() function as it is no longer needed. Moreover, the coreboot tables entry CB_TAG_MRC_CACHE does not exist anymore, as it is not created by the code. It was replaced by CBMEM_ID_MRCDATA entry, so MRCDATA should now be accessible through sysinfo structure field. Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M payloads/libpayload/arch/x86/coreboot.c M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c 4 files changed, 71 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/59491/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321 Gerrit-Change-Number: 59491 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/i2c/tpm/Kconfig: Reduce visibility of some configs
by Arthur Heymans (Code Review) 01 Dec '21

01 Dec '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59802 ) Change subject: drivers/i2c/tpm/Kconfig: Reduce visibility of some configs ...................................................................... drivers/i2c/tpm/Kconfig: Reduce visibility of some configs I2C bus and address of the TPM are typically fixed on hardware so there is no need to be able to configure this in menuconfig. Change-Id: I1b6afa68fe753fb76348e0461209d218b14df7cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/i2c/tpm/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/59802/1 diff --git a/src/drivers/i2c/tpm/Kconfig b/src/drivers/i2c/tpm/Kconfig index df622f0..dcf9060 100644 --- a/src/drivers/i2c/tpm/Kconfig +++ b/src/drivers/i2c/tpm/Kconfig @@ -31,12 +31,12 @@ default y config DRIVER_TPM_I2C_BUS - hex "I2C TPM chip bus" + hex default 0x9 # FIXME, workaround for Kconfig BS depends on I2C_TPM config DRIVER_TPM_I2C_ADDR - hex "I2C TPM chip address" + hex default 0x2 # FIXME, workaround for Kconfig BS depends on I2C_TPM -- To view, visit https://review.coreboot.org/c/coreboot/+/59802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b6afa68fe753fb76348e0461209d218b14df7cb Gerrit-Change-Number: 59802 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: driver/i2c: Add sx9360 driver
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Gwendal Grignou. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59608 ) Change subject: driver/i2c: Add sx9360 driver ...................................................................... Patch Set 2: (2 comments) File src/drivers/i2c/sx9360/sx9360.c: PS2: This looks very similar to `src/drivers/i2c/sx9324/sx9324.c`. Can it be unified? https://review.coreboot.org/c/coreboot/+/59608/comment/ccd3cfff_947c3d66 PS2, Line 61: describe described -- To view, visit https://review.coreboot.org/c/coreboot/+/59608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516 Gerrit-Change-Number: 59608 Gerrit-PatchSet: 2 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Dec 2021 10:19:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/tpm: Add override function for TPM I2C bus
by Arthur Heymans (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Christian Walter, Angel Pons, Arthur Heymans, EricR Lai. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59768 ) Change subject: drivers/i2c/tpm: Add override function for TPM I2C bus ...................................................................... Patch Set 4: (1 comment) File src/drivers/i2c/tpm/tis.c: https://review.coreboot.org/c/coreboot/+/59768/comment/7287131d_c3ac4abc PS4, Line 22: int __weak get_tpm_i2c_bus(void) : { : return CONFIG_DRIVER_TPM_I2C_BUS; : } I don't think a weak function is a good solution here. You could have wrongly configured, by forgetting to provide a stong symbol and the compiler would not complain. -- To view, visit https://review.coreboot.org/c/coreboot/+/59768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I658468ed3880de0a6b947c212fa8737956928c57 Gerrit-Change-Number: 59768 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 10:17:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Add SAR sensor for bugzzy
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Gwendal Grignou. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59609 ) Change subject: mb/google/dedede: Add SAR sensor for bugzzy ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59609/comment/dbdd65cc_ae30062d PS3, Line 7: mb/google/dedede mb/google/dedede/var/bugzzy: Add SAR sensor https://review.coreboot.org/c/coreboot/+/59609/comment/5526a9de_d0518b0f PS3, Line 9: 2 SX9360 SAR sensor 2 sensors? https://review.coreboot.org/c/coreboot/+/59609/comment/672d6bac_10587897 PS3, Line 9: Present 2 SX9360 SAR sensor for bugzzy. Please mention the busses they are added to. -- To view, visit https://review.coreboot.org/c/coreboot/+/59609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9feef9d132c60738bafb22ceb7d3468c798fab9b Gerrit-Change-Number: 59609 Gerrit-PatchSet: 3 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Dec 2021 10:15:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable CPPCv3 for Intel Alderlake
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59363 ) Change subject: soc/intel/alderlake: Enable CPPCv3 for Intel Alderlake ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59363/comment/b18bdc54_c6f8d433 PS5, Line 7: for Intel Alderlake Remove as it’s in the prefix. https://review.coreboot.org/c/coreboot/+/59363/comment/dc164ba5_c08eff26 PS5, Line 9: Alderlake Alder Lake https://review.coreboot.org/c/coreboot/+/59363/comment/26038782_d94341de PS5, Line 14: updated for ADL-P small and big cores correctly. What command did you use? -- To view, visit https://review.coreboot.org/c/coreboot/+/59363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaacd4a4ba953d8337f557903ed2ea9da4a60fb9 Gerrit-Change-Number: 59363 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 01 Dec 2021 10:13:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Fix S0i3 regression
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Lance Zhao, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Archana Patni, Michael Niewöhner, Ronak Kanabar. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59790 ) Change subject: mb/google/brya: Fix S0i3 regression ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59790/comment/280e2da5_226a8e43 PS2, Line 8: Please describe the problem. S0i3 does not work how? https://review.coreboot.org/c/coreboot/+/59790/comment/a89bfbd7_67d12948 PS2, Line 9: CB coreboot https://review.coreboot.org/c/coreboot/+/59790/comment/3efc18e0_81d506c8 PS2, Line 12: Please add the tag: Fixes: 0e905801 (soc/intel: transition full control over PM Timer from FSP to coreboot) https://review.coreboot.org/c/coreboot/+/59790/comment/d93cc4d8_41d449ea PS2, Line 14: TEST=Boot gimble to OS and verify S0i3 counter incrementing How can this be verified? -- To view, visit https://review.coreboot.org/c/coreboot/+/59790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1 Gerrit-Change-Number: 59790 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Archana Patni <archana.patni(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Archana Patni <archana.patni(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 10:12:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021